An FPGA-Based Ultra-High-Speed Object Detection Algorithm with Multi-Frame Information Fusion

Long, Xianlei; Hu, Shenhua; Hu, Yiming; Gu, Qingyi; Ishii, Idaku

doi:10.3390/s19173707

Cited by 16 publications

(12 citation statements)

References 28 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Our proposed design has a larger pixel per clock cycle value than most of the other hardware–software methods. The work by Long et al [ 13 ] has the highest pixel per clock cycle value. The reason is that in [ 13 ], the input of the system is 64 pixels per clock cycle, while others receive one pixel per clock cycle as an input.…”

Section: Results and Comparison With Other Workmentioning

confidence: 99%

“…The work by Long et al [ 13 ] has the highest pixel per clock cycle value. The reason is that in [ 13 ], the input of the system is 64 pixels per clock cycle, while others receive one pixel per clock cycle as an input. The work by Mizuno et al [ 18 ], which achieves the highest pixel per clock cycle value in the hardware–software co-design work (due to their highly parallel architecture), uses about twice the number of DSPs and about four times more LUT resources than our proposed design for the same image resolution.…”

Section: Results and Comparison With Other Workmentioning

confidence: 99%

“…There are several implementations of the HOG algorithm using pure hardware [ 11 , 12 , 13 , 14 ]. One of the benefits of implementing the HOG algorithm on hardware is of course speed enhancement.…”

Section: Related Work On Hardware–software Implementationsmentioning

confidence: 99%

“…Long et al [ 13 ] propose an ultra-high-speed implementation of the HOG algorithm for object detection. They use a high-speed vision platform which contains a high-speed camera FASTCAM SA-X2.…”

Section: Related Work On Hardware–software Implementationsmentioning

confidence: 99%

See 3 more Smart Citations

A Novel Hardware–Software Co-Design and Implementation of the HOG Algorithm

Ghaffari

Soleimani

et al. 2020

Sensors

View full text Add to dashboard Cite

The histogram of oriented gradients is a commonly used feature extraction algorithm in many applications. Hardware acceleration can boost the speed of this algorithm due to its large number of computations. We propose a hardware–software co-design of the histogram of oriented gradients and the subsequent support vector machine classifier, which can be used to process data from digital image sensors. Our main focus is to minimize the resource usage of the algorithm while maintaining its accuracy and speed. This design and implementation make four contributions. First, we allocate the computationally expensive steps of the algorithm, including gradient calculation, magnitude computation, bin assignment, normalization and classification, to hardware, and the less complex windowing step to software. Second, we introduce a logarithm-based bin assignment. Third, we use parallel computation and a time-sharing protocol to create a histogram in order to achieve the processing of one pixel per clock cycle after the initialization (setup time) of the pipeline, and produce valid results at each clock cycle afterwards. Finally, we use a simplified block normalization logic to reduce hardware resource usage while maintaining accuracy. Our design attains a frame rate of 115 frames per second on a Xilinx® Kintex® Ultrascale™ FPGA while using less hardware resources, and only losing accuracy marginally, in comparison with other existing work.

show abstract

Section: Results and Comparison With Other Workmentioning

confidence: 99%

Section: Results and Comparison With Other Workmentioning

confidence: 99%

Section: Related Work On Hardware–software Implementationsmentioning

confidence: 99%

Section: Related Work On Hardware–software Implementationsmentioning

confidence: 99%

See 2 more Smart Citations

A Novel Hardware–Software Co-Design and Implementation of the HOG Algorithm

Ghaffari

Soleimani

et al. 2020

Sensors

View full text Add to dashboard Cite

show abstract

“…Accessing the frame synchronization information from the image sensor in Verilog and reading an input pulse from a wire on a spare PMOD pin (at the appropriate voltage level of the carrier board) makes this relatively easy to implement. The large remaining resources can be utilized to create and test custom image processing algorithms such as real-time image classification [41] and object detection [42]. Some of this research requires separate high-speed and potentially expensive cameras as input, such as in [43] where two high-speed camera heads are used with a platform consisting of two FPGAs to create a high-speed vision system.…”

Section: Plos Onementioning

confidence: 99%

Development of a low-cost, user-customizable, high-speed camera

et al. 2020

View full text Add to dashboard Cite

High-speed imaging equipment can be an expensive investment, especially when certain applications require custom solutions. In this paper, we present a low-cost high-speed prototype camera built on a low-end Zynq-7000 System-on-Chip (SoC) platform and off-the-shelf components with the aim of removing the entry barrier into various high-speed imaging applications. The camera is standalone (does not require a host computer) and can achieve 211 frames per second (fps) at its maximum resolution of 1280x1024, and up to 2329 fps at a 256x256 resolution. With a current cost of only several hundred dollars and resource utilization of~5%, the open-source design's modularity and customizability allows users with sufficient hardware or programming experience to modify the camera to suit their needs, potentially driving the cost lower. This can be done by utilizing the large remaining programmable logic for custom image processing algorithms, creating user interface software on the CPU, attaching extensions through the peripheral Module connections, or creating custom carrier or daughter boards. The development and design of the camera is described and a figure-of-merit is presented to provide a value assessment of some available commercial high-speed cameras against which our camera is competitive. Finally, the camera was tested to record low frequency spatial vibration and was found to be useful in investigating phenotypes associated with aging in a leading animal model, the nematode (worm) Caenorhabditis elegans.

show abstract

From data inference to evidence fusion: A methodology for studying computer ethics at different levels

Piao,

Lin,

Song

et al. 2024

Comp Applic In Engineering

View full text Add to dashboard Cite

The rapid development and widespread use of computer technology in today's society have brought significant benefits and convenience to individuals and organizations. The study presents a concept for constructing a research framework in the realm of computer ethics impact. This involves the introduction of an information fusion model and the utilization of a Dempster–Shafer (D–S) evidence theory algorithm. The information fusion model aims to integrate multiple sources of evidence related to computer ethics, including expert opinions, public attitudes, and legal regulations. Furthermore, the experimental results show that the platform's impact perception was effective in reducing the number of individuals who consider computer ethics unnecessary from 40% to 3%. This finding highlights the potential of this platform for enhancing public awareness and understanding of computer ethics. In conclusion, the proposed information fusion model and D–S evidence theory algorithm offer a valuable tool for conducting early research on the construction of computer ethics. It is of utmost importance to delve into the uncontrollable facets of building computer ethics and to navigate the subject–object dilemma from the standpoint of computer users. This approach is essential in addressing the ethical dilemmas that have arisen due to the rapid advancement of computer technology in today's world. The novelty lies in the research methodology used in this study, substantial public perception change, ethical risk reduction, and subject–object issue in computer ethics resolution all substantially contribute to the field's influence on people, organizations, and societies.

show abstract

An FPGA-Based Ultra-High-Speed Object Detection Algorithm with Multi-Frame Information Fusion

Cited by 16 publications

References 28 publications

A Novel Hardware–Software Co-Design and Implementation of the HOG Algorithm

A Novel Hardware–Software Co-Design and Implementation of the HOG Algorithm

Development of a low-cost, user-customizable, high-speed camera

From data inference to evidence fusion: A methodology for studying computer ethics at different levels

Contact Info

Product

Resources

About