An FPGA-based reconfigurable IPSec AH core with efficient implementation of SHA-3 for high speed IoT applications

Abstract

The need for securing data across the Internet has become a fundamental issue over the last decade. The Internet protocol security (IPSec) standard has been developed as one solution to the problem of end‐to‐end secure communications. IPSec implementation is computationally intensive and can significantly limit the performance of high‐speed networks. To overcome this speed issue, hardware implementations of IPSec offer the best solution. This work presents a field programmable gate array‐based reconfigurable IPSec authentication header (AH) core. AH is one of the two main IPSec protocols, namely, AH and encapsulating security payload, and it supports both transport and tunnel modes of operations. For the AH protocol, a newly selected cryptographic hash function called secure hash algorithm‐3 (SHA‐3) is implemented and used in this work. SHA‐3 is implemented using a unique two‐phase implementation approach that combines all the steps of SHA‐3. The resultant equations, after combining the SHA‐3 steps, are implemented as a proposed high‐speed architecture, which results in data throughput in the gigabits per second range. The AH core proposed here outperforms other published techniques and is capable of supporting IPv4 datagrams for both modes of operation (transport and tunnel) and also can be used to provide security services for Internet of things applications that require high data throughput speeds. Copyright © 2016 John Wiley & Sons, Ltd.

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