An FPGA-based prototyping method for verification, characterization and optimization of LDPC error correction systems

Abstract

This paper introduces a methodology for forward error correction (FEC) architectures prototyping, oriented to system verification and characterization. A complete design flow is described, which satisfies the requirement for error-free hardware design and acceleration of FEC simulations. FPGA devices give the designer the ability to observe rare events, due to tremendous speed-up of FEC operations. A Matlab-based system assists the investigation of the impact of very rare decoding failure events on the FEC system performance and the finding of solutions which aim to parameters optimization and BER performance improvement of LDPC codes in the error floor region. Furthermore, the development of an embedded system, which offers remote access to the system under test and verification process automation, is explored. The presented here prototyping approach exploits the high-processing speed of FPGA-based emulators and the observability and usability of software-based models.

VLSI architectures for error correction in digital communication systems

“…More specifically, the overall test system consists of the Encoder, the AWGN Channel, the Multiple LDPC decoder, and the Errors Counter module (Fig. 4.3) [132]. BPSK modulated symbols are transmitted over the AWGN channel.…”

“…Ο αποκωδικοποιητής WiFi LDPC που ενσωματώνει τους προτεινόμενους αλγορίθμους και το δίκτυο RBR είναι πολύ αποδοτικός όσον αφορά την απόδοση αποκωδικοποίησης, την ταχύτητα, την επιφάνεια ολοκλήρωσης και την κατανάλωση ενέργειας, συγκρινόμενος με τους πιο πρόσφατους αποκωδικοποιητές της βιβλιογραφίας. Στο κεφάλαιο 7 αναλύεται μια μεθοδολογία για την πρωτοτυποποίηση αρχιτεκτονικών FEC [132]. Περιγράφεται μια ολοκληρωμένη ροή σχεδίασης, κατάλληλη για την επαλήθευση της ορθής λειτουργίας, τον χαρακτηρισμό και τη βελτιστοποίηση του συστήματος διόρθωσης σφαλμάτων.…”

“…Chapter 7 introduces a methodology for FEC architectures prototyping [132]. A complete design flow for system verification, characterization, and optimization is described.…”

“…The overall test system consists of an LDPC codec, an AWGN Channel, and a circuit for the BER performance evaluation (Fig. 7.2) [132]. The system has been designed in VHDL and mapped into Virtex7-XC7VX485T FPGA (VC707 evaluation board) using the Xilinx design flow.…”

“…Despite this, though, as shown in Table 6.8, the proposed decoder achieves very good results in terms of energy efficiency; very close to that of the work presented in [84], and more than 67% better than the rest of the reported decoders. [132], particularly suited for characterization of an LDPC error correction system, and readily applicable to different target implementations. A complete design flow is described, which satisfies the requirement for error-free hardware design and acceleration of FEC simulations.…”