An FPGA-Based Information Detection Hardware System Employing Multi-Match Content Addressable Memory

Le, Duc-Hung; Inoue, Katsumi; Sowa, Masahiro; Pham, Cong‐Kha

doi:10.1587/transfun.e95.a.1708

Cited by 14 publications

(8 citation statements)

References 12 publications

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“…Fig. 1(c) shows the architecture of a PE64 based on four one-hot encoders, which was designed by Le et al [7]. Each ENC converts a corresponding 16-bit group into 4-bit position and a control signal C decides whether the results are passed to next multiplexers.…”

Section: Previous Workmentioning

confidence: 99%

“…Several hierarchical architectures have been proposed to manage large-sized PEs whose sizes reach to several thousand bits. An approach adopting a set of one-hot encoders [7] or a set of specific comparator and sort circuits [8] are the cases in point. Nonetheless, those architectures require many resources to maintain a sufficient operating frequency (FREQ).…”

Section: Introductionmentioning

confidence: 99%

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A Scalable High-Performance Priority Encoder Using 1D-Array to 2D-Array Conversion

Nguyen

Pham

2017

IEEE Trans. Circuits Syst. II

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Abstract-In our prior study of an L-bit priority encoder (PE), a so-called one-directional-array to two-directional-array conversion method is deployed to turn an L-bit input data into an M × N-bit matrix. Following this, an N-bit PE and an M-bit PE are employed to obtain a row index and column index. From those, the highest priority bit of L-bit input data is achieved. This brief extends our previous work to construct a scalable architecture of high-performance large-sized PEs. An optimum pair of (M, N) and look-ahead signal are proposed to improve the overall PE performance significantly. The evaluation is achieved by implementing a variety of PEs whose L varies from 4-bit to 4096-bit in 180-nm CMOS technology. According to post-placeand-route simulation results, at PE size of 64 bits, 256 bits, and 2048 bits the operating frequencies reach 649 MHz, 520 MHz, and 370 MHz, which are 1.2 times, 1.5 times, and 1.4 times, as high as state-of-the-art ones.

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Section: Previous Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Scalable High-Performance Priority Encoder Using 1D-Array to 2D-Array Conversion

Nguyen

Pham

2017

IEEE Trans. Circuits Syst. II

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“…The Information Detection Hardware System was successfully designed on FPGA for 1-D data detection in our previous work [9]. The Information Detection Hardware System has been originally implemented on FPGA by using parallel CAM blocks and simple logic operations.…”

Section: A Structure Of the Systemmentioning

confidence: 99%

“…The CAM block is designed by using dual-port RAM blocks. The CAM design is also presented in more details by [9]. In any FPGA devices, memory resources and logic resources are limited.…”

Section: A Structure Of the Systemmentioning

confidence: 99%

A CAM-based Information Detection Hardware System for fast exact pattern matching

Cao

Inoue³

et al. 2013

2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS)

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A CAM-based Information Detection Hardware System for fast exact pattern matching is implemented on a hardware system with FPGA and ASIC. The system has a simple structure, does not employ any Central Processor Unit (CPU) as well as complicated algorithms. We take advantage of Content Addressable Memory (CAM) which has an ability of parallel multi-match mode for designing the system. The system is applied to fast pattern matching with various required search patterns without using any search principles. In this paper, the authors present the system for exact pattern matching on 2-D data.

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“…As the query length grows up to several thousand bits, making a check of them efficiently plays an essential role in IR. Multi-match priority encoder (MPE) has been widely utilized to obtain all matching bits in a query result to date [4,5]. Briefly, MPE is comprised of two primary modules, namely a priority encoder (PE) and a preprocessing circuit (PRE).…”

Section: Introductionmentioning

confidence: 99%

An FPGA approach for high-performance multi-match priority encoder

Nguyen

Pham

2016

IEICE Electron. Express

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In this paper, a scalable high-performance multi-match priority encoder (MPE) for information retrieval is presented. This approach deploys a new design architecture to construct the large-sized MPEs by using an 8-bit priority encoder as a basement. The experiments in an 8-bit MPE, 64-bit MPE, and 2,048-bit MPE prove that the achieved throughputs are 1.5 times, 1.7 times, and 1.4 times as high as those of previous works. Furthermore, a 4,096-bit MPE is fully operational in an information retrieval system and is capable of returning one match per clock cycle. At the operating frequency of 75 MHz, the processing time in worst and best case are 54.6 µs and 0.03 µs, respectively.

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An FPGA-Based Information Detection Hardware System Employing Multi-Match Content Addressable Memory

Cited by 14 publications

References 12 publications

A Scalable High-Performance Priority Encoder Using 1D-Array to 2D-Array Conversion

A Scalable High-Performance Priority Encoder Using 1D-Array to 2D-Array Conversion

A CAM-based Information Detection Hardware System for fast exact pattern matching

An FPGA approach for high-performance multi-match priority encoder

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