An FPGA based high performance optical flow hardware design for computer vision applications

Gültekin, Gökhan Koray; Saranlı, Afşar

doi:10.1016/j.micpro.2013.01.001

Cited by 40 publications

(13 citation statements)

References 20 publications

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“…In the article [ 26 ] a hardware realization of the Horn-Schunck algorithm in Cyclone II FPGA device was presented. The proposed fixed-point version was able to process 257 frames of 256 × 256 pixel resolution in one second (but with only one iteration).…”

Section: Previous Workmentioning

confidence: 99%

Efficient Hardware Implementation of the Horn-Schunck Algorithm for High-Resolution Real-Time Dense Optical Flow Sensor

Komorkiewicz

Kryjak

Gorgon

2014

Sensors

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This article presents an efficient hardware implementation of the Horn-Schunck algorithm that can be used in an embedded optical flow sensor. An architecture is proposed, that realises the iterative Horn-Schunck algorithm in a pipelined manner. This modification allows to achieve data throughput of 175 MPixels/s and makes processing of Full HD video stream (1, 920 × 1, 080 @ 60 fps) possible. The structure of the optical flow module as well as pre- and post-filtering blocks and a flow reliability computation unit is described in details. Three versions of optical flow modules, with different numerical precision, working frequency and obtained results accuracy are proposed. The errors caused by switching from floating- to fixed-point computations are also evaluated. The described architecture was tested on popular sequences from an optical flow dataset of the Middlebury University. It achieves state-of-the-art results among hardware implementations of single scale methods. The designed fixed-point architecture achieves performance of 418 GOPS with power efficiency of 34 GOPS/W. The proposed floating-point module achieves 103 GFLOPS, with power efficiency of 24 GFLOPS/W. Moreover, a 100 times speedup compared to a modern CPU with SIMD support is reported. A complete, working vision system realized on Xilinx VC707 evaluation board is also presented. It is able to compute optical flow for Full HD video stream received from an HDMI camera in real-time. The obtained results prove that FPGA devices are an ideal platform for embedded vision systems.

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Section: Previous Workmentioning

confidence: 99%

Efficient Hardware Implementation of the Horn-Schunck Algorithm for High-Resolution Real-Time Dense Optical Flow Sensor

Komorkiewicz

Kryjak

Gorgon

2014

Sensors

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“…CMLA's IPol website [4] also provides various codes of recent algorithms. Optimized implementations of optical flow algorithms were the subject of numerous works on FPGA [5], [6], [7], [8] and on GPU [9], [10], [11], [12], but few on CPU [11], [13]. It should also be noted that optical flow estimations based on machine learning are gaining in popularity in the scientific community [14], [15].…”

Section: Optical Flow Iterative Algorithmsmentioning

confidence: 99%

Energy and Execution Time Comparison of Optical Flow Algorithms on SIMD and GPU Architectures

Petreto¹,

Hennequin²,

Kœhler³

et al. 2018

2018 Conference on Design and Architectures for Signal and Image Processing (DASIP)

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This article presents and compares optimized implementations of two optical flow algorithms on several target boards comprising multi-core SIMD processors and GPUs. The two algorithms are Horn-Schunck (HS) and TV-L1, and have been chosen because they are both well-known, and because of their different computational complexity and accuracy. For both algorithms, we have made parallel optimized SIMD implementations, while HS has also been implemented on GPUs. For each algorithm, the comparison between the different versions and target boards is carried out in a two-dimensional fashion: in terms of computing speed-in order to achieve real-time computation-and in terms of energy consumption since we target embedded systems. The results show that for HS, the GPUs are the most efficient in both dimensions, able to process in realtime performances (25 frames per second) up to 8Mpix images for 0.35J per image, against 1.8Mpix images for 0.24J per image on CPU. The results also highlight the impact of optimizations on TV-L1: far slower than HS without optimization, it can almost match its performance after optimization on CPU, and can achieve real-time performances with 0.25J for 1.4Mpix images. We hope these results will help developers design optical flow embedded systems.

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“…It is based on a Xilinx Virtex-4 FPGA and generates 60 fps for image resolution of 640x480 pixels. An optical flow FPGA design is described in [27] using Altera's DE2-70 development board. The system receives images from a computer via RS-232 link and performs Horn and Schunk's method achieving the computation of the optical flow vector field for images of resolution 256x256 pixels in 3.89ms.…”

Section: Literature Surveymentioning

confidence: 99%

Design Details of a Low Cost and High Performance Robotic Vision Architecture

Vourvoulakis¹,

Kalomiros²,

Lygouras³

2015

IJC

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The implementation of an advanced real-time, low cost video processing platform capable of supporting a variety of demanding robotic applications is presented. The system is designed as an open project, accessible in full detail and has the potential to grow. It is based on a FPGA plus MCU architecture, allowing the implementation of combined fixed-point and 32-bit floating-point applications with optimized resource allocation. The presented platform is optimally integrated with appropriate controllers, like video-input frame grabbers for multiple camera applications, external SDRAM, as well as USB and VGA interfaces. The processing and interfacing capabilities of the proposed system are illustrated by implementing basic feature extraction and preprocessing tasks, achieving the display of processed video frames at a rate of 30 fps with resolution 640x480. The proposed architecture is evaluated in terms of resource usage, power consumption and cost. Potential applications are also discussed.

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An FPGA based high performance optical flow hardware design for computer vision applications

Cited by 40 publications

References 20 publications

Efficient Hardware Implementation of the Horn-Schunck Algorithm for High-Resolution Real-Time Dense Optical Flow Sensor

Efficient Hardware Implementation of the Horn-Schunck Algorithm for High-Resolution Real-Time Dense Optical Flow Sensor

Energy and Execution Time Comparison of Optical Flow Algorithms on SIMD and GPU Architectures

Design Details of a Low Cost and High Performance Robotic Vision Architecture

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