An FPGA-based hardware-efficient fault-tolerant astrocyte-neuron network

Johnson, Anju P.; Halliday, David M.; Millard, Alan G.; Tyrrell, Andy M.; Timmis, Jon; Liu, Junxiu; Harkin, Jim; McDaid, Liam; Karim, Shvan

doi:10.1109/ssci.2016.7850175

Cited by 21 publications

(12 citation statements)

References 17 publications

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“…It is evident from Figure 3-A that the fault repair happens at a rate of ms, proving to be a very efficient scheme for real world applications. This is a very important capability for the fault-tolerant hardware systems due to the distributed, fine-grained repair capability which will yield a significantly enhanced performance over conventional approaches [17], [18].This enhancement is also due to ability of the system to run at an accelerated time scale.…”

Section: B Partial Faultsmentioning

confidence: 99%

Fault-Tolerant Learning in Spiking Astrocyte-Neural Networks on FPGAs

Johnson

Liu

Millard

et al. 2018

2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID)

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Abstract-The paper presents a neuromorphic system implemented on a Field Programmable Gate Array (FPGA) device establishing fault tolerance using a learning method, which is a combination of the Spike-Timing-Dependent Plasticity (STDP) and Bienenstock, Cooper, and Munro (BCM) learning rules. The rule modulates the synaptic plasticity level by shifting the plasticity window, associated with STDP, up/down the vertical axis as a function of postsynaptic neural activity. Specifically when neurons are inactive, either early on in the normal learning phase or when a fault occurs, the window is shifted up the vertical axis (open), leading to an increase in firing rate of the postsynaptic neuron. As learning progresses, the plasticity window moves down the vertical axis until the desired postsynaptic neuron firing rate is established. Experimental results are presented to show the effectiveness of proposed approach in establishing fault tolerance. The system can maintain the network performance with at least one nonfaulty synapse. Finally, we discuss a robotic application utilizing the proposed architecture.

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Section: B Partial Faultsmentioning

confidence: 99%

Fault-Tolerant Learning in Spiking Astrocyte-Neural Networks on FPGAs

Johnson

Liu

Millard

et al. 2018

2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID)

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“…The detailed hardware model of the astrocyte-neuron selfrepairing unit is presented in [12]. In this work, we use a simplification of this model which has greater than 90% hardware efficiency compared to [12], and at the same time achieves the same level of fault repair [7]. This model simplifies the complex chemical processes inside an astrocyte by retaining the key features of direct negative feedback and indirect positive feedback in the self-repairing unit shown in Fig.…”

Section: A Reduced Model Of Bio-inspired Self Repair Unitmentioning

confidence: 99%

“…The synapse processes the signals DSE and eSP , and makes a decision on the current to be injected into the neuron. More details of this model is presented in [7].…”

Section: A Reduced Model Of Bio-inspired Self Repair Unitmentioning

confidence: 99%

Homeostatic fault tolerance in spiking neural networks utilizing dynamic partial reconfiguration of FPGAs

Johnson

Liu

Millard

et al. 2017

2017 International Conference on Field Programmable Technology (ICFPT)

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We present a novel methodology that addresses the problem of faults in synapses of a spiking neural network using astrocyte regulation, inspired by recovery processes in the brain. Since Field Programmable Gate Arrays (FPGAs) are widely used for neural network applications, we aim to achieve fault tolerance in an astrocyte-neuron unit implemented on an FPGA. A fault is considered as a reduction in transmission probability of a synapse, leading to reduced spiking activity. Our novel repair mechanism exploits Dynamic Partial Reconfiguration (DPR) of the FPGA Clock Management Tiles (CMTs) to increase the clock frequency of neurons with reduced synaptic input, which restores the firing rate to pre-fault levels. We demonstrate the repair methodology on a spiking neural network implemented on an FPGA. The system maintains effective functional behavior with a loss of up to 99% of the original synaptic inputs to a neuron. Our repair mechanism has minimal hardware overhead with the tuning circuit (repair unit) which consumes only 0.8215% of the complete design and therefore supports scalable implementations. Additionally, the overall architecture has a minimal impact on power consumption (1.371W ). The work opens up a novel way to utilize the capabilities of modern hardware to mimic homeostatic self-repair behavior achieving fault recovery.

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“…architecture having self-repairing mechanism to increase the system [9]- [14]. Moreover, several digital circuits focused on neuron-astrocyte interactions and synaptic plasticity are also developed by other researchers [3], [8], [15]- [17].…”

Section: Introductionmentioning

confidence: 99%

Digital Implementation of the Two-Compartmental Pinsky–Rinzel Pyramidal Neuron Model

Rahimian

Zabihi

Amiri

et al. 2018

IEEE Trans. Biomed. Circuits Syst.

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It is believed that brain-like computing system can be achieved by the fusion of electronics and neuroscience. In this way, the optimized digital hardware implementation of neurons, primary units of nervous system, play a vital role in neuromorphic applications. Moreover, one of the main features of pyramidal neurons in cortical areas is bursting activities that has a critical role in synaptic plasticity. The Pinsky-Rinzel model is a nonlinear two-compartmental model for CA3 pyramidal cell that is widely used in neuroscience. In this paper, a modified Pinsky-Rinzel pyramidal model is proposed by replacing its complex nonlinear equations with piecewise linear approximation. Next, a digital circuit is designed for the simplified model to be able to implement on a low-cost digital hardware, such as field-programmable gate array (FPGA). Both original and proposed models are simulated in MATLAB and next digital circuit simulated in Vivado is compared to show that obtained results are in good agreement. Finally, the results of physical implementation on FPGA are also illustrated. The presented circuit advances preceding designs with regards to the ability to replicate essential characteristics of different firing responses including bursting and spiking in the compartmental model. This new circuit has various applications in neuromorphic engineering, such as developing new neuroinspired chips.

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An FPGA-based hardware-efficient fault-tolerant astrocyte-neuron network

Cited by 21 publications

References 17 publications

Fault-Tolerant Learning in Spiking Astrocyte-Neural Networks on FPGAs

Fault-Tolerant Learning in Spiking Astrocyte-Neural Networks on FPGAs

Homeostatic fault tolerance in spiking neural networks utilizing dynamic partial reconfiguration of FPGAs

Digital Implementation of the Two-Compartmental Pinsky–Rinzel Pyramidal Neuron Model

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