An FPGA-Based Hardware Accelerator for Energy-Efficient Bitmap Index Creation

Nguyen, Xuan-Thuan; Hoang, Trong-Thuc; Nguyen, Hong-Thu; Inoue, Katsumi; Pham, Cong‐Kha

doi:10.1109/access.2018.2816039

Cited by 13 publications

(8 citation statements)

References 20 publications

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“…This is 37.12% less then the previous implemented system based on software pattern recognition algorithms [26]. Hardware accelerators, containing content addressable memory and index 8-bit and 16-bit in parallel with each clock cycle, were implemented in [27]. This system consumes as low as 6.76% and 3.28% of energy compared to CPU and GPU-based designs respectively.…”

Section: Introductionmentioning

confidence: 93%

Static and Dynamic Algorithms for Terrain Classification in UAV Aerial Imagery

et al. 2019

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The ability to precisely classify different types of terrain is extremely important for Unmanned Aerial Vehicles (UAVs). There are multiple situations in which terrain classification is fundamental for achieving a UAV's mission success, such as emergency landing, aerial mapping, decision making, and cooperation between UAVs in autonomous navigation. Previous research works describe different terrain classification approaches mainly using static features from RGB images taken onboard UAVs. In these works, the terrain is classified from each image taken as a whole, not divided into blocks; this approach has an obvious drawback when applied to images with multiple terrain types. This paper proposes a robust computer vision system to classify terrain types using three main algorithms, which extract features from UAV's downwash effect: Static textures-Gray-Level Co-Occurrence Matrix (GLCM), Gray-Level Run Length Matrix (GLRLM) and Dynamic textures-Optical Flow method. This system has been fully implemented using the OpenCV library, and the GLCM algorithm has also been partially specified in a Hardware Description Language (VHDL) and implemented in a Field Programmable Gate Array (FPGA)-based platform. In addition to these feature extraction algorithms, a neural network was designed with the aim of classifying the terrain into one of four classes. Lastly, in order to store and access all the classified terrain information, a dynamic map, with this information was generated. The system was validated using videos acquired onboard a UAV with an RGB camera.Several methods for terrain classification have been proposed in different works. Texture algorithms, such as those proposed in [2][3][4][5], have been widely recommended to emphasize the high and low frequencies of the images, supporting image classification. Other algorithms use color information to classify terrains, such as presented in [6], which is able to distinguish four different terrain types within an image. During this process, each channel's pixel is divided by the square root of its own three channels intensity. The final result will emphasize the color that most represents the terrain type (eg, blue for water). Additionally, frequency domain [7,8], segmentation [6,9,10], bayesian network [11], and Hyperspectal Images [12] can also be used in terrain classification.Other types of sensors such as LiDAR [13][14][15][16] can complement the classification decision. Algorithms that use laser scanners proved to be qualified to accurately distinguish between water and non-water terrains [13][14][15][16]. However, shallow water terrains increase the decision error due to laser reflection, which leads to a misclassification as non-water terrain.Although prior research work has proposed many good solutions for terrain classification, there is still a gap regarding the study of dynamic terrain. The previously mentioned algorithms suffer from a high sensitivity to changes in the environment, mainly due to changes in brightness, color and texture. Recent works [17,18] ...

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Section: Introductionmentioning

confidence: 93%

Static and Dynamic Algorithms for Terrain Classification in UAV Aerial Imagery

et al. 2019

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“…With W = 4 and Rule = 4, we need 2 W =24 =16 registers and number of bits of each register = number of rules = 4. Thus, decoding the Basic Rule table in Table 2 we need a RAM of size 2 4 x4 = 16x4 (16 registers with each register having a width of 4 bits). When applying principle 1 for writing to RAM, we have the results shown in Table 3.…”

Section: Basic Ideasmentioning

confidence: 99%

“…With priority encoding, output of TCAM is the highest prioritized result. TCAM is widely uses in networking routers such as translations-look-aside buffers (TLBs) [3] caches in microprocessors, database accelerators in big data analytics [4] and in pattern recognition [5].…”

Section: Introductionmentioning

confidence: 99%

Efficient TCAM design based on dual port SRAM on FPGA

Triet

Ngo

Trinh

et al. 2021

IJEECS

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<span><span>Ternary content addressable memory (TCAM) is a memory that allows high speed searching for data. Not only it is acknowledged as associative memory/storage but also TCAM can compare input searching content (key) against a collection of accumulated data and return the matching address which compatible with this input search data. SRAM-based TCAM utilizes and allocates blocks RAM to perform application of TCAM on FPGA hardware. This paper presents a design of 480×104 bit SRAM-based TCAM on altera cyclone IV FPGA. Our design achieved lookup rate over 150 millions input search data and update speed at 75 million rules per second. The architecture is configurable, allowing various performance trade-offs to be exploited for different ruleset characteristics</span>.</span>

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“…Conventional CAM (on ASIC) has the drawback of high power consumption, limited storage density, non-scalability, and high implementation cost [3,13], compared with a random-access memory (RAM) which has high storage density and lower power consumption. One CAM cell requires 9-10 transistors, while one RAM cell needs only 6 transistors which makes conventional CAM power inefficient and limits its storage density.…”

Section: Introductionmentioning

confidence: 99%

Zi-CAM: A Power and Resource Efficient Binary Content-Addressable Memory on FPGAs

2019

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Content-addressable memory (CAM) is a type of associative memory, which returns the address of a given search input in one clock cycle. Many designs are available to emulate the CAM functionality inside the re-configurable hardware, field-programmable gate arrays (FPGAs), using static random-access memory (SRAM) and flip-flops. FPGA-based CAMs are becoming popular due to the rapid growth in software defined networks (SDNs), which uses CAM for packet classification. Emulated designs of CAM consume much dynamic power owing to a high amount of switching activity and computation involved in finding the address of the search key. In this paper, we present a power and resource efficient binary CAM architecture, Zi-CAM, which consumes less power and uses fewer resources than the available architectures of SRAM-based CAM on FPGAs. Zi-CAM consists of two main blocks. RAM block (RB) is activated when there is a sequence of repeating zeros in the input search word; otherwise, lookup tables (LUT) block (LB) is activated. Zi-CAM is implemented on Xilinx Virtex-6 FPGA for the size 64 × 36 which improved power consumption and hardware cost by 30 and 32%, respectively, compared to the available FPGA-based CAMs.

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An FPGA-Based Hardware Accelerator for Energy-Efficient Bitmap Index Creation

Cited by 13 publications

References 20 publications

Static and Dynamic Algorithms for Terrain Classification in UAV Aerial Imagery

Static and Dynamic Algorithms for Terrain Classification in UAV Aerial Imagery

Efficient TCAM design based on dual port SRAM on FPGA

Zi-CAM: A Power and Resource Efficient Binary Content-Addressable Memory on FPGAs

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