An FPGA-based ATE extension module for low-cost multi-GHz memory test

Abstract

This paper describes an ATE extension module that enables a low-cost test system to be applied to advanced (multi-GHz) memories. The target application is for testing memories with data rates above 3.2Gbps. The test module uses state-of-the-art FPGAs for economical autonomous pattern synthesis and comparison under the high-level supervision of a low-cost "host" test platform (ATE). The FPGA logic capabilities are complemented by custom 4-channel "pin electronics" (PE) modules with I/O performance comparable to advanced ATE. The PE modules provide input/output/bidirectional signal conditioning, including amplitude, format, timing, and preemphasis, and a "shadow sampler."

SoftMC: Practical DRAM Characterization Using an FPGA-Based Infrastructure

“…FPGA-Based Testing Infrastructures. Several prior works propose FPGA-based DRAM testing infrastructures [47,50,59]. Unfortunately, all of them lack exibility and/or a simple user interface, and none are open-source.…”

“…Hou et al [47] propose an FPGAbased test platform whose capability is limited to analyzing only the data retention time of the DRAM cells. Another work [59] develops a custom memory testing board with an FPGA chip, speci cally designed to test memories at a very high data rate. However, it requires low-level knowledge to develop FPGA programs, and even then o ers only limited exibility in de ning a test routine.…”