An extended model to support detailed GPGPU reliability analysis

Du, Boyang; Condia, Josie E. Rodriguez; Reorda, M. Sonza

doi:10.1109/dtis.2019.8735047

Cited by 17 publications

(11 citation statements)

References 19 publications

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“…This work extends [6] by proposing and evaluating improvements to save execution time and memory footprint. Also, the experiments presented in this work are performed in an optimized version of the FlexGrip, the soft-core GPGPU used in the previous work, which has been enhanced to correct some limitations and functional restrictions presented in the original version of the model [12].…”

Section: Background a Related Workmentioning

confidence: 99%

Evaluating Software-based Hardening Techniques for General-Purpose Registers on a GPGPU

Goncalves¹,

Azambuja²,

Condia³

et al. 2020

2020 IEEE Latin-American Test Symposium (LATS)

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Graphics Processing Units (GPUs) are considered a promising solution for high-performance safety-critical applications, such as self-driving cars. In this application domain, the use of fault tolerance techniques is mandatory to detect or correct faults, since they must work properly even in the presence of faults. GPUs are designed with aggressive technology scaling, which makes them susceptible to faults caused by radiation interference, such as the Single Event Upsets (SEUs), which can lead the system to a failure, and that is unacceptable in safety-critical applications. In this paper, we evaluate different software-based hardening techniques developed to detect SEUs in GPUs general-purpose registers and propose optimizations to improve performance and memory utilization. The techniques are implemented in four case-study applications and evaluated in a general-purpose soft-core GPU based on the NVIDIA G80 architecture. A fault injection campaign is performed at register transfer level to assess the fault detection potential of the implemented techniques. Results show that the proposed improvements can be tailored for different scenarios, helping engineers in navigating the design space of hardened GPGPU applications.

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Section: Background a Related Workmentioning

confidence: 99%

Evaluating Software-based Hardening Techniques for General-Purpose Registers on a GPGPU

Goncalves¹,

Azambuja²,

Condia³

et al. 2020

2020 IEEE Latin-American Test Symposium (LATS)

Self Cite

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“…We performed fault simulation experiments on a GPGPU model using four representative applications to extend conclusions and to evaluate the effects of permanent faults. Flex-Grip [43], [44] was selected as a GPGPU model to perform the experiments. This open-source model is described in VHDL and includes the basic modules employed in modern GPGPUs for program kernel execution.…”

Section: Effects Of Permanent Faults In the Scheduler Memorymentioning

confidence: 99%

An On-Line Testing Technique for the Scheduler Memory of a GPGPU

2020

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The highly parallel processing capabilities and reduced power performance of General Purpose Graphics Processing Units (GPGPUs) have been crucial factors for their massive use in multiple fields, such as multimedia and high-performance computing applications. Nowadays, more demanding areas, such as automotive, employ GPGPU devices where safety and reliability are mandatory design constraints. Nevertheless, the structural complexity, the transistor density, and the implementation in the latest silicon technologies introduce challenges to match safety and reliability requirements. In these technologies, wear-out and aging are factors that may significantly increase the occurrence of permanent faults during the lifetime operation. Moreover, these faults may generate unacceptable misbehaviors during the execution of an application. These constraints require devising new methods for in-field fault detection, thus verifying the integrity and correct behavior of the device during its whole operational life. This work proposes a technique to generate functional self-test programs targeting the detection of permanent static faults in the memory of the warp scheduler of a GPGPU. The proposed technique can translate fault primitives, which represent the effect of faults in a memory cell, into self-test functions and programs composed of a sequence of operations to excite the fault in the memory and to propagate its effects to a visible location, thus detecting its presence. We focused on the memory in the warp scheduler because it represents a crucial module for the device operation. Furthermore, this memory is present in each Streaming Multiprocessor (SM) of a GPGPU. Some experimental results to validate the method have been gathered, resorting to the NVIDIA Visual Profiler and the Nsight Debugger using the NVIDIA-GEFORCE GTX GPU platform and a structural fault simulator. The CUDA programming environment was used to implement the test procedures. INDEX TERMS Functional test, general purpose graphics processing units (GPGPUs), memory test, software-based self-test (SBST).

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“…For this work, we employ this improved version of the model. Readers may refer to [18] for a full list of supported formats and instructions in FlexGrip and additional details of the performed modifications. Inside the SM, one warp scheduler controller manages the execution of instructions and controls the operation of threads.…”

Section: The Flexgrip Gpgpu Modelmentioning

confidence: 99%

A dynamic hardware redundancy mechanism for the in-field fault detection in cores of GPGPUs

Condia¹,

Narducci²,

Reorda³

et al. 2020

2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems (DDECS)

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In the past, in most General-Purpose Graphic Processing Units (GPGPUs) application fields (e.g., multimedia and gaming), the reliability features were not so relevant. Nowadays, GPGPUs are used in new domains, such as the automotive one, where reliability plays a significant role. In this work, we describe a dynamic duplication with a comparison (DDWC) mechanism intended to harden the Scalar Processor (SP) units located in the Streaming multiprocessors (SM) of a GPGPU. The proposed mechanism targets the permanent faults that may arise inside the SPs. One additional SP unit is included in the system to compute redundantly the same operations of a selected SP. Results are compared, and possible failures detected. A custom reconfiguration instruction allows the dynamic selection of the target SP to be monitored. Experimental results show that the proposed mechanism introduces a limited area overhead while it provides a significant increase in the in-field fault detection capabilities of the GPGPU. Its flexibility allows selecting the best trade-off between fault detection latency and performance overhead.

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An extended model to support detailed GPGPU reliability analysis

Cited by 17 publications

References 19 publications

Evaluating Software-based Hardening Techniques for General-Purpose Registers on a GPGPU

Evaluating Software-based Hardening Techniques for General-Purpose Registers on a GPGPU

An On-Line Testing Technique for the Scheduler Memory of a GPGPU

A dynamic hardware redundancy mechanism for the in-field fault detection in cores of GPGPUs

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