An Exploration Framework for Efficient High-Level Synthesis of Support Vector Machines: Case Study on ECG Arrhythmia Detection for Xilinx Zynq SoC

Tsoutsouras, Vasileios; Koliogeorgi, Konstantina; Xydis, Sotirios; Soudris, Dimitrios

doi:10.1007/s11265-017-1230-1

Cited by 21 publications

(14 citation statements)

References 34 publications

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“…Another HLS-based implementation with a hardware/ software co-design is recently presented in [66], focusing on design space exploration. A systematic two-level methodology and prototype framework is proposed for realizing an efficient HLS-based SVM IP.…”

Section: Development Tool-based Architecturesmentioning

confidence: 99%

“…Only four researchers utilize the recent Xilinx series-7 devices [23,31,51,55]. One unique research work is discriminated by exploiting the hybrid architecture of the recent Zynq-7 SoC platform and using the latest UltraFast HLS design methodology [59][60][61][62][63][64] followed by a recent study for design space exploration based on SVM implementation in [66,67].…”

Section: Preliminary Analysismentioning

confidence: 99%

“…They aim to reduce hardware area while maintaining high accuracy. Moreover, Afifi et al [60,61] have studied the trade-off between the speed/acceleration and hardware resources utilization/area with applying some different hardware architectures (HLS optimization directives), followed by similar analysis study focusing on design space exploration presented in [66,67]. As a result of applying different techniques for reducing hardware complexity and gaining acceleration, some implementations reported some loss in the classification accuracy rate [21,32,57,[67][68][69][73][74][75].…”

Section: Preliminary Analysismentioning

confidence: 99%

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FPGA Implementations of SVM Classifiers: A Review

2020

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Support vector machine (SVM) is a robust machine learning model with high classification accuracy. SVM is widely utilized for online classification in various real-time embedded applications. However, implementing SVM classification algorithm for an embedded system is challenging due to intensive and complicated computations required. Several works attempted to optimize performance and cost by implementing SVM in hardware, especially on field-programmable gate array (FPGA) as it is a promising platform for meeting challenging embedded systems constraints. This article presents a comprehensive survey of hardware architectures used for implementing SVM on FPGA over the period 2010-2019. We performed a critical analysis and comparison of existing works with in-depth discussions around limitations, challenges, and research gaps. We concluded that the primary research gap is overcoming the challenging trade-off between meeting critical embedded systems constraints and achieving efficient and precise classification. Finally, some future research directions are proposed, aiming to address such research gaps.

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Section: Development Tool-based Architecturesmentioning

confidence: 99%

Section: Preliminary Analysismentioning

confidence: 99%

Section: Preliminary Analysismentioning

confidence: 99%

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FPGA Implementations of SVM Classifiers: A Review

2020

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“…This suggests, that these parts of the transformation fail to capture the distinct characteristics of the investigated problem. Summing up, we consider SVM classifier as the best choice given that it provides the maximum accuracy, while its structure allows for optimizations aiming at execution with real-time constraints [15].…”

Section: B Employing the Decision Making Framework In The Case Of Ecmentioning

confidence: 99%

From edge to cloud: Design and implementation of a healthcare Internet of Things infrastructure

Masouros

Bakolas

Tsoutsouras

et al. 2017

2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)

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Lately, the advancement in circuit technology combined with the design of low cost embedded devices have resulted in an infiltration of the latter into everyday humans' lives. To exploit the full potential of ubiquitous embedded devices, a network is used for their inter-communication, offering advanced real-time monitoring. This paradigm, known as Internet of Things (IoT), is steadily consolidated and promises to offer a wide variety of applications. However, with the adoption of IoT, new challenges arise, such as the design of architectures able to support the requirements of the new applications. Towards this goal, we explore a three layered architecture, able to acquire, process and store Healthcare data as well as to provide real-time decision making. We use ECG signal arrhythmia detection as our use case evaluation scenario, and compare different techniques for wireless communication, storage and data classification. Experimental results show that, our architecture provides realtime decision making, with an average delay of 15 μs and that different communication technologies achieved to provide up to 10% lower power consumption on the monitoring devices. 1

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“…The experiment achieves a 1.7× improvement, and the total power is less than 380 mW. Tsoutsouras V uses Vivado High-Level Synthesis (HLS) to implement hardware acceleration of SVM for electrocardiogram arrhythmia detection, achieving 78× acceleration compared to software execution [22]. Based on the Zynq platform, Benkuan Wang et al used the Least Squares Support Vector Machine (LSSVM) for online fault diagnosis of an Unmanned Aerial Vehicle (UAV) [23,24].…”

Section: Introductionmentioning

confidence: 99%

Research and Implementation of ε-SVR Training Method Based on FPGA

Liu

et al. 2019

Electronics

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Online training of Support Vector Regression (SVR) in the field of machine learning is a computationally complex algorithm. Due to the need for multiple iterative processing in training, SVR training is usually implemented on computer, and the existing training methods cannot be directly implemented on Field-Programmable Gate Array (FPGA), which restricts the application range. This paper reconstructs the training framework and implementation without precision loss to reduce the total latency required for matrix update, reducing time consumption by 90%. A general ε-SVR training system with low latency is implemented on Zynq platform. Taking the regression of samples in two-dimensional as an example, the maximum acceleration ratio is 27.014× compared with microcontroller platform and the energy consumption is 12.449% of microcontroller. From the experiments for the University of California, Riverside (UCR) time series data set. The regression results obtain excellent regression effects. The minimum coefficient of determination is 0.996, and running time is less than 30 ms, which can meet the requirements of different applications for real-time regression.

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An Exploration Framework for Efficient High-Level Synthesis of Support Vector Machines: Case Study on ECG Arrhythmia Detection for Xilinx Zynq SoC

Cited by 21 publications

References 34 publications

FPGA Implementations of SVM Classifiers: A Review

FPGA Implementations of SVM Classifiers: A Review

From edge to cloud: Design and implementation of a healthcare Internet of Things infrastructure

Research and Implementation of ε-SVR Training Method Based on FPGA

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