An experimental single-chip data flow CPU

Uvieghara, G.A.; Hwu, Wen-mei W.; Nakagome, Y.; Jeong, Deog‐Kyoon; Lee, D.; Hodges, D.A.; Patt, Yale N.

doi:10.1109/vlsic.1990.111124

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Cited by 5 publications

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“…The critical storage structures on the chip, the Node Tables (aka reservation stations) and the Checkpointed Register Alias Table (used for handling precise exceptions) intrigued Uvieghara. Under the direction of Professor Hodges and with the consulting of Wen-mei Hwu, Uvieghara proceeded to investigate the viability of these storage structures for a current implementable design [4].…”

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confidence: 99%

Retrospective: HPSm, a high performance restricted data flow architecture having minimal functionality

Hwu

Patt

1998

25 Years of the International Symposia on Computer Architecture (Selected Papers)

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mentioning

confidence: 99%

Retrospective: HPSm, a high performance restricted data flow architecture having minimal functionality

Hwu

Patt

1998

25 Years of the International Symposia on Computer Architecture (Selected Papers)

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“…It also controls the computation of data in the functional units and the transfer of data and results to and from the storage units. Two key limitations of the synchronous approach, similar to those for Von Neumann's 'stored program control', are: the execution of the subsequent instructions even when the operands of the latter are available [24]. This clearly results in the failure to exploit potential parallelism that may be inherent in the program.…”

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confidence: 99%