Murray Hill, New Jersey 07974 U.S.A. Successful operation of a 300 megabit/second 2 level path length modtulator at 57 GHz has been reported previously.1 If the repeater spacing is set to give adequate performance in the high and low frequency channels of a broadband waveguide system, channels closer to the middle of the band may have sufficient system margin to allow 4 level operation. This paper gives a preliminary report on a 4 level path length modulator wherein two 300 megabit/second data streams are multiplexed onto a mm-wave channel. Figure 1 is a schematic diagram of the modulator and a laboratory detector. The mm-wave oscillator output is fed into two PIN diode switches connected in tandem through circulators. The first switch changes the phase of the transmitter signal by 900 and the second switch by 1800. The state of these switches in the mth time slot is represented by a two-bit number s(m), where the first bit describes the 1800 switch and the second bit the 900 switch, 0 representing a closed state and 1 an open state. If t(m) represents the bits in the two data streams in the mth time slot, differentially coherent phase shift keying of t(m) is obtained if2 s(m) = s(m-l) + t(m) One exclusive OR circuit and two flip-flops perform this operation. They-are included in the logic circuit indicated in Fig. 1. The RF phase of the transmitted signal may be 0 9Q0, 1800 or 2700 relative to that in the preceding time slot.In the detector, the signal is fed without delay to two hybrids. It is also fed to the same hybrids through other paths which contain a, common dela.y of one time slot (3.33 ns delay for 300 megabaud signals) and phase increments of ±450.A detector is attached to the difference arm of each hybrid.If the phase difference between successive time slots is zero, corresponding to t(m) = 00, each detector output is close to a null and the small outputs obtained are read as 00. t(m) -10 gives a phase difference of 1800 and each detect.or output is close to the greatest possible output, interpreted as 11. Examination of the other two conditions shows that t(m) =-01 is read as 01, while t(m) = 11 is read as 10. Thus, one detector gives the first bit of t(m) while the second bit of t(m) is obtained by exclusive OR combination of the two detector outputs. This conversion was actually performed at the transmitter in part of the logic circuit indicated in Fig. 1. Thus, the logic circuit consists of two exclusive OR circuits and two flip-flops.
