An Experimental Evaluation of Fault-Tolerant FPGA-Based Robot Controller

Podivinsky, Jakub; Lojda, Jakub; Kotásek, Zdenĕk

doi:10.1109/ewdts.2018.8524627

Cited by 1 publication

(1 citation statement)

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“…Guruprasad et al [20] present the fault and congestion-free NoC design where faults are tolerated in NoC using Error Code Correction techniques with better fault coverage. Podivinsky et al [21] present the hardware-based robot controller with a fault-tolerant mechanism, which evaluates single and multiple fault-injection analysis with electronic failures.…”

Section: Related Workmentioning

confidence: 99%

Performance Analysis of Transient Fault-Injection and Fault-Tolerant System for Digital Circuits on FPGA

N¹,

Dinesha²

2020

IJACSA

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Fault-Tolerant System is necessary to improve the reliability of digital circuits with the presence of Fault Injection and also improves the system performance with better Fault Coverage. In this work, an efficient Transient Fault-Injection system (FIS) and Fault-Tolerant System (FTS) are designed for digital circuits. The FIS includes Berlekamp Massey Algorithm (BMA) based LFSRs, with fault logic followed by one -hot-encoder register, which generates the faults. The FTS is designed using Triple-Modular-Redundancy (TMR) and Dual Modular-Redundancy (DMR). The TMR module is designed using the Majority Voter Logic (MVL), and DMR is designed using Self-Voter Logic (SVL) for digital circuits such as synchronous and asynchronous circuits. The four different MVL approaches are designed in the TMR module for digital circuits. The FIS-FTS module is designed on Xilinx-ISE 14.7 environment and implemented on Artix-7 FPGA. The synthesis results include chip area, gate count, delay, and power are analyzed along with fault tolerance, and coverage for given digital circuits. The fault tolerance is analyzed using Modelsim-simulator. The FIS-FTS module covers an average of 99.17% fault coverage for both synchronous and asynchronous circuits.

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Section: Related Workmentioning

confidence: 99%