An exact MCMC accelerator under custom precision regimes

Liu, Shuanglong; Mingas, Grigorios; Bouganis, Christos-Savvas

doi:10.1109/fpt.2015.7393138

Cited by 11 publications

(18 citation statements)

References 9 publications

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“…The main benefit of accelerating CNN models in FPGAs comes from the fact that CNNs are robust to low bitwidth quantization [11]. Instead of using the default double or single floating point precision in CPU, fixed-point precision can be used in FPGA-based CNN accelerator to achieve an efficient design optimized for performance and power efficiency [9,10]. In this work, we implement our proposed design with 16 bit fixed-point which has been shown to achieve almost the same accuracy as floating point in the inference stage, in order to allow optimizations for high parallelism mentioned in the above section.…”

Section: Optimizationsmentioning

confidence: 99%

Optimizing CNN-Based Hyperspectral Image Classification on FPGAs

Liu

Chu

Wang

et al. 2019

Lecture Notes in Computer Science

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Hyperspectral image (HSI) classification has been widely adopted in applications involving remote sensing imagery analysis which require high classification accuracy and real-time processing speed. Methods based on Convolutional neural networks (CNNs) have been proven to achieve state-of-the-art accuracy in classifying HSIs. However, CNN models are often too computationally intensive to achieve real-time response due to the high dimensional nature of HSI, compared to traditional methods such as Support Vector Machines (SVMs). Besides, previous CNN models used in HSI are not specially designed for efficient implementation on embedded devices such as FPGAs. This paper proposes a novel CNN-based algorithm for HSI classification which takes into account hardware efficiency. A customized architecture which enables the proposed algorithm to be mapped effectively onto FPGA resources is then proposed to support real-time on-board classification with low power consumption. Implementation results show that our proposed accelerator on a Xilinx Zynq 706 FPGA board achieves more than 70× faster than an Intel 8-core Xeon CPU and 3× faster than an NVIDIA GeForce 1080 GPU. Compared to previous SVM-based FPGA accelerators, we achieve comparable processing speed but provide a much higher classification accuracy.

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Section: Optimizationsmentioning

confidence: 99%

Optimizing CNN-Based Hyperspectral Image Classification on FPGAs

Liu

Chu

Wang

et al. 2019

Lecture Notes in Computer Science

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“…This article extends our prior work [18], by (1) investigating and comparing alternative custom precision likelihood construction approximates targeting improved performance (i.e. effective samples per second) and (2) proposing a method to maximize the performance of the algorithm by selecting the optimal arithmetic precision based on performing short MCMC pre-runs on a set of candidate precisions.…”

Section: Introductionmentioning

confidence: 95%

“…In our prior work, we showed the FPGA architecture of the CF-MCMC Algorithm where only a single highprecision datapath was utilised in the design [18]. Building on the previous architecture, a more generic design which utilizes multiple high-precision datapaths is presented here and it is depicted in Figure 2.…”

Section: Proposed Hardware Architecturementioning

confidence: 99%

“…Given the logistic regression likelihood function in Equation (12) as an example, the previous proposal in [18] of the lower bound function (13) is based on the error bound ε 1 of the whole function which is provided by Gappa++.…”

Section: Lower Bound Function Constructionmentioning

confidence: 99%

“…LC n (θ) ≤ LD n (θ). In order to achieve this in a custom precision setting, in our prior work [18] we proposed to use the tool Gappa++ [25] which determines and verifies numerical behaviour, and particularly rounding error in computations with floating point operations. The tool manipulates logical formulas stating the enclosures of expressions in some intervals.…”

Section: Lower Bound Function Constructionmentioning

confidence: 99%

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An Unbiased MCMC FPGA-Based Accelerator in the Land of Custom Precision Arithmetic

Liu

Mingas

Bouganis

2017

IEEE Trans. Comput.

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Abstract-Markov Chain Monte Carlo (MCMC) based methods have been the main tool used for Bayesian Inference by practitioners and researchers due to their flexibility and theoretical properties that guarantee unbiased sampling-based estimates. Nevertheless, with the availability of large data sets and the constant need to develop more complex models that better capture the targeted problem, significant computational challenges have been presented. Current approaches, based on multi-core CPUs, GPUs, and FPGAs, aim to accelerate the execution time of the MCMC methods using subsampling techniques or custom precision arithmetic, resulting to biased estimates. In this work, a novel FPGA-based construction is proposed that utilises the custom precision support of FPGA devices in order to accelerate the computations, guaranteeing at the same time asymptotically unbiased estimates. Key to this approach is the extension of the parameter space by an extra parameter that indicates the required precision in the computation of the likelihood of a data point. The work proposes an FPGA architecture for the above algorithm, as well as discuss its tuning for maximising the performance of the system. The performance of the FPGA-mapped sampler is evaluated using two Bayesian logistic regression case studies of varying complexity, which show significant speedups compared to existing FPGA-and CPU-based works that utilise double floating point arithmetic, without any bias on the sampling-based estimates.

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Speeding Up MCMC by Efficient Data Subsampling

Quiroz

Kohn

Villani

et al. 2018

Journal of the American Statistical Association

117

159

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We propose Subsampling MCMC, a Markov Chain Monte Carlo (MCMC) framework where the likelihood function for n observations is estimated from a random subset of m observations. We introduce a highly efficient unbiased estimator of the loglikelihood based on control variates, such that the computing cost is much smaller than that of the full log-likelihood in standard MCMC. The likelihood estimate is bias-corrected and used in two dependent pseudo-marginal algorithms to sample from a perturbed posterior, for which we derive the asymptotic error with respect to n and m, respectively. We propose a practical estimator of the error and show that the error is negligible even for a very small m in our applications. We demonstrate that Subsampling MCMC is substantially more efficient than standard MCMC in terms of sampling efficiency for a given computational budget, and that it outperforms other subsampling methods for MCMC proposed in the literature.

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An exact MCMC accelerator under custom precision regimes

Cited by 11 publications

References 9 publications

Optimizing CNN-Based Hyperspectral Image Classification on FPGAs

Optimizing CNN-Based Hyperspectral Image Classification on FPGAs

An Unbiased MCMC FPGA-Based Accelerator in the Land of Custom Precision Arithmetic

Speeding Up MCMC by Efficient Data Subsampling

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