An exact algorithm for selecting partial scan flip-flops

Chakradhar, Srimat; Balakrishnan, Arun A.; Agrawal, Vishwani D.

doi:10.1145/196244.196285

Cited by 114 publications

(20 citation statements)

References 19 publications

(12 reference statements)

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“…This problem is related to the minimum feedback vertex set problem, which despite being NP-hard, can be solved efficiently for large problem instances using heuristic methods [2], [8], [11]. In order to reduce the overhead due to system-level I/O pins and interconnect, the feedback loops should be broken in such a way that buses with the least bitwidth are multiplexed to primary I/Os.…”

Section: System-level Test Strategymentioning

confidence: 99%

A synthesis-for-transparency approach for hierarchical and system-on-a-chip test

Chakrabarty

2003

IEEE Trans. VLSI Syst.

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Abstract-Test data propagation through modules and test vector translation are two major challenges encountered in hierarchical testing. We propose a new synthesis-for-test approach in which multiplexers are embedded in the behavioral models of the various modules constituting a hierarchical system. This approach can also be applied to system-on-a-chip designs in which synthesizable models are available for the embedded cores. The embedded multiplexers provide complete single-cycle transparency, thereby offering a straightforward yet effective solution to the problems of test data propagation and test vector translation. In order to determine module I/O bitwidths for single-cycle transparency, a global analysis is carried out using a graph-theoretic framework and an optimization method based on integer linear programming. Case studies using high-level synthesis benchmarks and an industrial-strength benchmark show that synthesis for transparency introduces very little area and performance overhead.Index Terms-Embedded multiplexer, I/O bitwidth, parallel test access, single-cycle transparency, test reuse.

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Section: System-level Test Strategymentioning

confidence: 99%

A synthesis-for-transparency approach for hierarchical and system-on-a-chip test

Chakrabarty

2003

IEEE Trans. VLSI Syst.

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“…Partial-scan mthods can be categorized as: structure based [7][8][9][10][11], testability-measure based [12], and test-generation based [13] methods. Of the three, structure based methods have been most successful.…”

Section: Introductionmentioning

confidence: 99%

SPARTAN: a spectral and information theoretic approach to partial-scan

Khan

Bushnell

Devanathan

et al. 2007

2007 IEEE International Test Conference

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“…(2) The algorithm is not useful if one is interested in enumerating all or a large subset of minimum FVS solutions. Another interesting experiment was reported recently in [3]. They reported results on a simple branch-and-bound algorithm for vertex selection with known graph reductions/partitioning applied after each selection.…”

Section: Introductionmentioning

confidence: 99%

Implicit computation of minimum-cost feedback-vertex sets for partial scan and other applications

Ashar

Malik

1994

Proceedings of the 31st Annual Conference on Design Automation Conference - DAC '94

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The contribution of this paper is an implicit method for computing the minimum cost feedback vertex set for a graph. For an arbitrary graph, we efficiently derive a Boolean function whose satisfying assignments directly correspond to feedback vertex sets of the graph. Importantly, cycles in the graph are never explicitly enumerated, but rather, are captured implicitly in this Boolean function. This function is then used to determine the minimum cost feedback vertex set. Even though computing the minimum cost satisfying assignment for a Boolean function remains an NP-hard problem, we can exploit the advances made in the area of Boolean function representation in logic synthesis to tackle this problem efficiently in practice for even reasonably large sized graphs. The algorithm has obvious application in flip-flop selection for partial scan. Our algorithm was the first to obtain the MFVS solutions for many benchmark circuits.

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An exact algorithm for selecting partial scan flip-flops

Cited by 114 publications

References 19 publications

A synthesis-for-transparency approach for hierarchical and system-on-a-chip test

A synthesis-for-transparency approach for hierarchical and system-on-a-chip test

SPARTAN: a spectral and information theoretic approach to partial-scan

Implicit computation of minimum-cost feedback-vertex sets for partial scan and other applications

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