An evolutionary approach to implement logic circuits on three dimensional FPGAs

Rahimi, H.; Jahanirad, Hadi

doi:10.1016/j.eswa.2021.114780

Cited by 5 publications

(1 citation statement)

References 41 publications

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“…To conduct assessment, we utilized simulations on large circuits from the VTR benchmark suite [25]. To ascertain the ILV count, each benchmark circuit underwent a Min-cut partitioning process, following a similar approach as described in [26]. In the clustering of ILVs, it is assumed that these ILVs are distributed on the chip according to a uniform distribution.…”

Section: Resultsmentioning

confidence: 99%

A Clustering-BIST Design for Inter-Layer Vias in 3D ICs Based on Walking Pattern Approach

Menbari,

Rahimi,

Jahanirad

et al. 2023

Preprint

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<p> In the realm of 3D monolithic integrated circuits, inter-layer vias are prone to defects during fabrication, assembly, and operation that necessitate robust Built-In Self-Test solutions. This paper introduces an innovative BIST design aimed at the detection and localization of different types of faults in irregularly placed ILVs using a walking pattern methodology. In the proposed BIST methodology, the ILVs are clustered based on the fault occurrence probability distribution. Then, an effective detection approach is developed for all stuck-at faults, bridging faults, and almost all multiple faults in a single cluster. This approach allows designers to adjust different parameters such as fault coverage percentage, fault localization, and test time in alignment with specific requisites. The proposed BIST method reduces test configurations to two and test time to just 20 cycles by dividing ILVs into more clusters, overcoming a key limitation of recent approach. This methodology also demonstrates improved efficiency in terms of power consumption, area, and hardware utilization, particularly for large-scale benchmarks. For instance, when considering LU32PEENG and the scenario where ILVs are divided into 64 clusters, the power, area, and hardware overhead are 0.82% and 1.03%, and 1.14%, respectively. </p>

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Section: Resultsmentioning

confidence: 99%

A Clustering-BIST Design for Inter-Layer Vias in 3D ICs Based on Walking Pattern Approach

Menbari,

Rahimi,

Jahanirad

et al. 2023

Preprint

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Design of Low Power Multiplier with Less Area Using Quaternary Carry Increment Adder for New-Fangled Processors

Gavaskar¹,

Malathi²,

Ravivarma³

et al. 2022

Wireless Pers Commun

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Multiplication is one of the basic functions in Digital Signal Processing (DSP) applications. Multiplier plays an important role in Arithmetic and Logic Unit (ALU), which is a critical element in the processors. The e ciency of the multiplier takes part a crucial task in the execution of the processor. The performance of the multiplier depends on the adder circuit. The addition operation is the fundamental operation used in most of the digital circuits. Power, delay and area are the main issues in VLSI circuits. E ciency of a VLSI circuit can be improved by rectifying any of these issues. Quaternary Signed Digits (QSD) placed on adders have better e ciency when compared to traditional binary logic. QSD based Carry Look Ahead (CLA) Adder is used to increase the e ciency with reference to power and delay. The proposed method uses Quaternary Carry Increment Adder in order to improve the power and reduce the delay of the existing Quaternary Carry Look Ahead Adder. Tanner EDA is the simulation tool used to design the circuits and the power, delay and power-delay product of the designed circuits are measured using it.

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A Novel Approach for Offline and Online Application-Dependent testing of FPGA interconnects

Menbari,

Rahimi,

Jahanirad

2023

2023 5th Iranian International Conference on Microelectronics (IICM)

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An evolutionary approach to implement logic circuits on three dimensional FPGAs

Cited by 5 publications

References 41 publications

A Clustering-BIST Design for Inter-Layer Vias in 3D ICs Based on Walking Pattern Approach

A Clustering-BIST Design for Inter-Layer Vias in 3D ICs Based on Walking Pattern Approach

Design of Low Power Multiplier with Less Area Using Quaternary Carry Increment Adder for New-Fangled Processors

A Novel Approach for Offline and Online Application-Dependent testing of FPGA interconnects

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