An Evaluation of Using CCIX for Cache-Coherent Host-FPGA Interfacing

Tamimi, Sajjad; Stock, Florian; Koch, Andreas; Bernhardt, Arthur; Petrov, Ilia

doi:10.1109/fccm53951.2022.9786103

Cited by 8 publications

(1 citation statement)

References 4 publications

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“…A number of other studies have also explored this problem [11,17,32] confirming that the advantages a hardware accelerator can bring are bound by the ability to generate enough load on it, often leading to a situation where the accelerated system is larger than the initial one. This issue is one of the reasons why new processor architectures are emerging that try to avoid these bottlenecks [7,8] and new standards for peripheral interconnects are appearing [6,24,30].…”

Section: Introductionmentioning

confidence: 99%

The Difficult Balance Between Modern Hardware and Conventional CPUs

Maschi

Alonso

2023

Proceedings of the 19th International Workshop on Data Management on New Hardware

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Research has demonstrated the potential of accelerators in a wide range of use cases. However, there is a growing imbalance between modern hardware and the CPUs that submit the workload. Recent studies of GPUs on real systems have shown that many servers are often needed per accelerator to generate a high enough load so the computing power is leveraged. This fact is often ignored in research, although it often determines the actual feasibility and overall efficiency of a deployment. In this paper, we conduct a detailed study of the possible configurations and overall cost efficiency of deploying an FPGA-based accelerator on a commercial search engine. First, we show that there are many possible configurations balancing the upstream system and the way the accelerator is configured. Of these configurations, not all of them are suitable in practice, even if they provide some of the highest throughput. Second, we analyse the cost of a deployment capable of sustaining the required workload of the commercial search engine. We examine deployments both on-premises and in the cloud with and without FPGAs and with different board models. The results show that, while FPGAs have the potential to significantly improve overall performance, the performance imbalance between their host CPUs and the FPGAs can make the deployments economically unattractive. These findings are intended to inform the development and deployment of accelerators by showing what is needed on the CPU side to make them effective and also to provide important insights into their end-to-end integration within existing systems. CCS CONCEPTS• Hardware → Hardware accelerators; • Computer systems organization → Cloud computing; Client-server architectures; Heterogeneous (hybrid) systems.

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