An enhancement transient response of capless LDO with improved dynamic biasing control for SoC applications

Ameziane, Hatim; Qjidaa, Hassan; Kamal, Zared; Zouak, M.

doi:10.1109/icm.2015.7438003

Cited by 6 publications

(3 citation statements)

References 7 publications

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“…A series of techniques have been proposed to improve the transient response of CL-LDO [ 12 , 13 , 14 , 15 , 16 , 17 ]. Using a flipped voltage follower (FVF) to separate the dominant poles in conventional LDO is one of the most popular methods.…”

Section: Introductionmentioning

confidence: 99%

“…To enhance both the transient and stability, Li et al proposed a CL-LDO based on dual-active feedback frequency compensation that ultimately guarantees stable operation in a load range of 0 to 100 mA [ 14 ]. In [ 17 ], the authors use modified Miller compensation with the insertion of a sensor amplifier stage to inject more transient current in the biasing circuit. This method feeds the regulator to rapidly charge the power PMOS gate capacitance and improves the fast transient response.…”

Section: Introductionmentioning

confidence: 99%

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A Fast Transient Response Capacitor-Less LDO with Transient Enhancement Technology

Chen,

Sun,

Wang

et al. 2024

Micromachines

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This paper proposes a fast transient load response capacitor-less low-dropout regulator (CL-LDO) for digital analog hybrid circuits in the 180 nm process, capable of converting input voltages from 1.2 V to 1.8 V into an output voltage of 1 V. The design incorporates a rail-to-rail input and push–pull output (RIPO) amplifier to enhance the gain while satisfying the requirement for low power consumption. A super source follower buffer (SSFB) with internal stability is introduced to ensure loop stability. The proposed structure ensures the steady-state performance of the LDO without an on-chip capacitor. The auxiliary circuit, or transient enhancement circuit, does not compromise the steady-state stability and effectively enhances the transient performance during sudden load current steps. The proposed LDO consumes a quiescent current of 47 µA and achieves 25 µV/mA load regulation with a load current ranging from 0 to 20 mA. The simulation results demonstrate that a settling time of 0.2 µs is achieved for load steps ranging from 0 mA to 20 mA, while a settling time of 0.5 µs is attained for load steps ranging from 20 mA to 0 mA, with an edge time of 0.1 µs.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Fast Transient Response Capacitor-Less LDO with Transient Enhancement Technology

Chen,

Sun,

Wang

et al. 2024

Micromachines

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“…High-performance PMICs with high stability, fast dynamic response and high efficiency have become more important. With the advantages of simple structure, low quiescent current, wide bandwidth and noise suppression ability [1][2][3][4][5], LDOs are widely used in wearable intelligence devices, memory, etc. [6][7][8][9][10].…”

Section: Introductionmentioning

confidence: 99%

A Capacitorless Flipped Voltage Follower LDO with Fast Transient Using Dynamic Bias

Chen

Wang

et al. 2022

Electronics

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The output capacitorless low-dropout regulator (OCL-LDO) has developed rapidly in recent years. This paper presents a flipped voltage follower (FVF) OCL-LDO with fast transient response. By adding a dynamic bias circuit to the FVF circuit, the proposed LDO has the ability to quickly adjust the gate voltage of the power transistor, without extra power consumption. The proposed LDO was designed in 0.18 μm CMOS process. The simulation results show that the recovery time is 52 ns when the load changes from 0.1 mA to 20 mA with a slew rate of 20 mA/ps, while the quiescent current is 92 μA with 1 V regulated output. The undershoot and overshoot voltage are 242 mV and 250 mV, respectively.

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Fractional Order Low–Dropout Voltage Regulator

Rocke

Ramlal

Singh

2016

2016 8th International Conference on Computational Intelligence and Communication Networks (CICN)

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An enhancement transient response of capless LDO with improved dynamic biasing control for SoC applications

Cited by 6 publications

References 7 publications

A Fast Transient Response Capacitor-Less LDO with Transient Enhancement Technology

A Fast Transient Response Capacitor-Less LDO with Transient Enhancement Technology

A Capacitorless Flipped Voltage Follower LDO with Fast Transient Using Dynamic Bias

Fractional Order Low–Dropout Voltage Regulator

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