An enhanced thermo-compression bonding process to address warpage in 3D integration of large die on organic substrates

Sakuma, Katsuyuki; Tunga, Krishna; Webb, Buck; Ramachandran, Koushik; Interrante, M. J.; Liu, Hsichang; Angyal, M.; Berger, Daniel; Knickerbocker, John; Iyer, Subramanian S.

doi:10.1109/ectc.2015.7159611

Cited by 32 publications

(3 citation statements)

References 13 publications

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“…Therefore, only three steps are necessary for the 3D stacking process, which is simpler than the conventional flip chip bonding process. [27][28][29][30] First, the fluxing underfill was dispensed on substrates or interposers with a syringe. In some cases, it can be dispensed on a chip to be stacked.…”

Section: Design Fabrication and Stacking Process Of Si Interposersmentioning

confidence: 99%

Characterization of transmission lines with through-silicon-vias and bump joints on high-resistivity Si interposers for RF three-dimensional modules

Choi¹,

Eom²,

Bae³

et al. 2016

Jpn. J. Appl. Phys.

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Microstrip lines and coplanar waveguides (CPWs) for RF three-dimensional (3D) modules were characterized on high-resistivity Si interposers: 2,000 Ω·cm. The diameter and thickness of through-silicon-vias (TSVs) in Si interposers were 50 and 250 µm, respectively. A signal TSV around five ground TSVs, and a signal solder bump around five ground solder bumps were designed to obtain the vertical transitions with low electrical loss between the transmission lines. For the 3D interconnections between Si interposers, a fluxing underfill material was developed and used as a preapplied underfill during the thermocompression bonding. The S-parameters of transmission lines and stacked transmission lines were measured from 0.5 to 10 GHz using a vector network analyzer (VNA) and de-embedded so that their electrical losses were obtained and compared. By comparing with the electrical loss of the transmission line on low-temperature cofired ceramics (LTCC), we found that both transmission lines were sufficiently good for applications in RF 3D modules.

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Section: Design Fabrication and Stacking Process Of Si Interposersmentioning

confidence: 99%

Characterization of transmission lines with through-silicon-vias and bump joints on high-resistivity Si interposers for RF three-dimensional modules

Choi¹,

Eom²,

Bae³

et al. 2016

Jpn. J. Appl. Phys.

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show abstract

“…1 shows the two areas of interest which were modeled: chip-to-chip and chip-to-laminate. Cross section of a 2.5D structure [1] The fine pitch configuration, characterized by closely spaced interconnects, exacerbates challenges related to thermal expansion mismatch, stress concentration, and fatigue. A robust finite-element model is essential to comprehensively 2 assess the package's response to these challenges and guide design improvements.…”

Section: Introductionmentioning

confidence: 99%

The Impact of AI on Contact Resistance and Its Suitability in Fine Pitch Interconnects

Lie,

Raghavan,

Perfecto

et al. 2024

IMAPSource Proceedings

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Integration issues for a three-dimensional (3D) interconnect in a Face-to-Face (F2F) configuration are discussed. In particular, the effect of AI and organic dielectrics under the bump and their effect in chip-package-interaction (CPI) stresses as well as AI contact resistance issues that arise as the interconnection pitch is decreased. This paper will present a finite-element model created to study the stresses in advanced 3D microelectronic package. To assess the reliability of the 3D packages a submodeling approach is used to capture the CPI stresses. The modeling study presented indicates that it is beneficial to continue using AI pads as it has significatly lower stresses compared to copper pads/vias. In the second portion of the paper, the effect of PBO developer on AI corrosion is presented. Reactive ion etching (RIE) chemistries and wet chemistries were optimized using contact resistance as the success metric. Process robustness was achieved by decoupling the hard dielectric opening from the PBO via opening. Time of Flight Secondary Ion Mass Spectrometry (ToF-SIMS), Scanning Electron Microscopy (SEM), X-ray Photoelectron Spectroscopy (XPS) analysis were used to add clarity to the bump contact resistance values.

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“…2 Because of the high melting points of Sn solders (∼230 • C), serious warping can occur in microelectronics packages because there is a large mismatch in the coefficient of thermal expansion (CTE) between the die and the substrate, 3 and this warping effect can lead to open joints, bridging, or non-wetting of solder bumps that degrade device performance. 4,5 Another reliability issue is delamination of the low-k dialectic layer. 6 Because of the high modulus of copper pillars, which transmits more mechanical stress to the die during the bonding process, and high thermal stress that results from CTE mismatch between the die and substrate, the thermo-mechanical stress causes severe damage to the inherently weak low-k dielectric layer, resulting in delamination of the layer.…”

mentioning

confidence: 99%

Materials Merging Mechanism of Microfluidic Electroless Interconnection Process

Yang

Hung

et al. 2018

J. Electrochem. Soc.

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A low-temperature, pressureless bonding process, referred to as the microfluidic electroless interconnection process, has been developed for chip-stacking applications, in which electroless Ni plating is employed to bond copper pillars in an attempt to reduce the risk of thermo-mechanical damage during the assembly process. Copper pillar joints with a low standoff height were used to assess the bonding performance of the microfluidic electroless interconnection process on a smaller scale. The results showed that a striking lamellar structure formed in the deposits when electroless Ni solution was fed into a microfluidic platform intermittently, and through this visible structure, the bonding mechanism of the process can be characterized fully. Preliminary results showed that a high level of plating uniformity across the die could be obtained using the microfluidic interconnection process, and that the copper pillars were joined completely by electroless Ni plating without voids or seams. Further, it was found that the process is able to compensate not only for non-uniform copper surfaces, but also for the misalignment of copper pillars, which provides a competitive edge over other bonding methods. In addition, the direct shear test showed that the bond strength of the electroless Ni bonds was quite strong.

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An enhanced thermo-compression bonding process to address warpage in 3D integration of large die on organic substrates

Cited by 32 publications

References 13 publications

Characterization of transmission lines with through-silicon-vias and bump joints on high-resistivity Si interposers for RF three-dimensional modules

Characterization of transmission lines with through-silicon-vias and bump joints on high-resistivity Si interposers for RF three-dimensional modules

The Impact of AI on Contact Resistance and Its Suitability in Fine Pitch Interconnects

Materials Merging Mechanism of Microfluidic Electroless Interconnection Process

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