An Enhanced Secured FPGA based DES

Abstract

In this paper we demonstrate an efficient and compact reconfigurable hardware implementation of the Data Encryption Standard (DES) algorithm. Our design was implemented on FPGA of device VirtexEXCV400e. As a strategy to reduce the associated design critical path, we utilized a parallel structure that allowed us to compute all the eight DES S-boxes simultaneously. The testing of theimplemented design shows that it is possible to generate data in 16 clock cycles when non-pipelined approach is employed. Whenpipelined approach is employed on the other hand, 17 clocksignals are required for the initial phase only, and one clocksignal is sufficient afterwards for each data generation cycle. TheVery High Speed Integrated Circuit Hardware DescriptionLanguage (VHDL) is used to program the design.

Synthesis of 64-Bit Triple Data Encryption Standard Algorithm using VHDL

“…In [10], efficient and compact reconfigurable synthesis of the Data Encryption Standard (DES) algorithm [10] and synthesis using device VirtexEXCV400e.…”