An Enhanced Gate-Grounded NMOSFET for Robust ESD Applications

Du, Feibo; Song, Shiyu; Hou, Fei; Song, Wenqiang; Chen, Long; Liu, Zhiwei; Liou, Juin J.

doi:10.1109/led.2019.2926103

Cited by 14 publications

(7 citation statements)

References 9 publications

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“…4 a, b, respectively. To avoid the parasitic effects associated with the substrate, P-type guard rings (PGR) are employed in both structures, and each PGR is connected to GND [ 21 ]. The central axle of ND is aligned with the NWELL/PWELL junction, and the parameter D1 is used to describe half of the ND length, while D2 is the length of SAB region.…”

Section: Resultsmentioning

confidence: 99%

Robust and Latch-Up-Immune LVTSCR Device with an Embedded PMOSFET for ESD Protection in a 28-nm CMOS Process

et al. 2020

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Low-voltage-triggered silicon-controlled rectifier (LVTSCR) is expected to provide an electrostatic discharge (ESD) protection for a low-voltage integrated circuit. However, it is normally vulnerable to the latch-up effect due to its extremely low holding voltage. In this paper, a novel LVTSCR embedded with an extra p-type MOSFET called EP-LVTSCR has been proposed and verified in a 28-nm CMOS technology. The proposed device possesses a lower trigger voltage of ~ 6.2 V and a significantly higher holding voltage of ~ 5.5 V with only 23% degradation of the failure current under the transmission line pulse test. It is also shown that the EP-LVTSCR operates with a lower turn-on resistance of ~ 1.8 Ω as well as a reliable leakage current of ~ 1.8 nA measured at 3.63 V, making it suitable for ESD protections in 2.5 V/3.3 V CMOS processes. Moreover, the triggering mechanism and conduction characteristics of the proposed device were explored and demonstrated with TCAD simulation.

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Section: Resultsmentioning

confidence: 99%

Robust and Latch-Up-Immune LVTSCR Device with an Embedded PMOSFET for ESD Protection in a 28-nm CMOS Process

et al. 2020

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“…With the scaling down of CMOS processes, the challenges of the electrostatic discharge (ESD) protection for integrated circuits (IC) become more severe [ 1 ]. The gate-grounded NMOS (GGNMOS), which was previously one of the most widely used ESD protection devices in CMOS processes, is invalid in advanced CMOS technologies due to its inadequate robustness [ 2 , 3 , 4 ]. Therefore, the researchers began to turn their attentions to the lateral silicon-controlled rectifier (LSCR) thanks to its higher level of robustness.…”

Section: Introductionmentioning

confidence: 99%

MOSs-String-Triggered Silicon-Controlled Rectifier (MTSCR) ESD Protection Device for 1.8 V Application

et al. 2023

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In this work, a new low voltage-triggered silicon-controlled rectifier named MTSCR is realized in a 65 nm CMOS process for low voltage-integrated circuits electrostatic discharge (ESD) protections. The MTSCR incorporates an external NMOSs-string, which drives the internal NMOS (INMOS) of MTSCR to turn on, and then the INMOS drive SCR structure to turn on. Compared with the existing low trigger voltage (Vt1) ESD component named diodes-string-triggered SCR (DTSCR), the MTSCR can realize the same low Vt1 characteristic but less area penalty of ~44.3% reduction. The results of the transmission line pulsing (TLP) measurement shows that the MTSCR possesses above 2.42 V holding voltage (Vh) and a low Vt1 of ~5.03 V, making it very suitable for the ESD protections for 1.8 V input/output (I/O) ports in CMOS technologies.

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“…With the miniaturization of semiconductor feature size and the advancement of integrated circuits, catastrophic ElectroStatic Discharge (ESD) events can seriously deteriorate chip reliability [1][2][3][4][5][6]. Conventional diode structures and Gate-Grounded NMOS (GGNMOS) structures always require a large silicon area to achieve a good ESD robustness [7][8][9][10]. By contrast, silicon controlled rectifiers (SCRs) have been widely used due to their highest robustness per unit area [11][12][13][14][15][16][17][18][19][20].…”

Section: Introductionmentioning

confidence: 99%

Analysis of current aggregation in gate-control dual direction silicon controlled rectifier

Zhong

Wang

Jin

et al. 2021

IEICE Electron. Express

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The current aggregation mechanism created by the gate structure is proposed for electrostatic discharging (ESD). Through device simulation, the size-expanded gate structure in gate-control dual-direction silicon controlled rectifier (GC-DDSCR) is found to aggregate the surface parasitic current path and the main SCR current path. The SCR current path is consequently twisted and extended to increase the holding voltage (Vh). Two GC-DDSCRs are fabricated in a 0.5μm CMOS technology and tested by transmission line pulse (TLP). The Vh increases from 13.84V to 16.44V as the gate size expands from 2.5μm to 4.5μm. The mechanism of current aggregation is verified.

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An Enhanced Gate-Grounded NMOSFET for Robust ESD Applications

Cited by 14 publications

References 9 publications

Robust and Latch-Up-Immune LVTSCR Device with an Embedded PMOSFET for ESD Protection in a 28-nm CMOS Process

Robust and Latch-Up-Immune LVTSCR Device with an Embedded PMOSFET for ESD Protection in a 28-nm CMOS Process

MOSs-String-Triggered Silicon-Controlled Rectifier (MTSCR) ESD Protection Device for 1.8 V Application

Analysis of current aggregation in gate-control dual direction silicon controlled rectifier

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