An enhanced AES algorithm using cascading method on 400 bits key size used in enhancing the safety of next generation internet of things (IOT)

Ritambhara,; Gupta, Alka; Jaiswal, Manjit

doi:10.1109/ccaa.2017.8229877

Cited by 13 publications

(7 citation statements)

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“…The last related work set in comparison to this paper was published in the ICCCA [15]. In the author's proposal, the efficiency of AES algorithm has been improved via utilizing sequential 200-bit plain text as input and 400 bits as key in cascaded format.…”

Section: Simulation and Resultsmentioning

confidence: 99%

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Real-time FPGA implementation of concatenated AES and IDEA cryptography system

Hassan¹,

Hamza²

2021

IJEECS

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<span>The data encryption is one of the most critical issues in the communication system design. Nowadays, many encryption algorithms are being updated to keep pace with the remarkable progress in the communication field. The advanced encryption standard (AES) is a common algorithm that has proved its efficacy. The main drawback of AES is that it uses too simple algebraic structures, since every block is always encrypted in the same way that makes the hacking process possible if the hacker captures the key and the uses S-Box in the input stage. This especially applies to the unwired communication systems where chances of hacking exceed those found in the wired systems. The paper proposes a security enhancement method that is based on utilizing concatenated AES and international data encryption algorithm (IDEA) algorithms. Upon applying the proposed algorithm, the hacking process becomes a great challenge. The paper incorporates the real-time FPGA implementation of the proposed algorithm in the encryption and the decryption stages. Besides, the paper presents a clear analysis of the system’s performance.</span>

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Section: Simulation and Resultsmentioning

confidence: 99%

“…However, this enhancement consumes more resources and power. Ritambhara [15], the authors present an enhanced AES algorithm that applies cascading method on a key whose size is 400 bits. For promoting the safety of internet of things' next generation, the article proposes an algorithm that comprises diffusion of AES algorithm.…”

Section: Introductionmentioning

confidence: 99%

Real-time FPGA implementation of concatenated AES and IDEA cryptography system

Hassan¹,

Hamza²

2021

IJEECS

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“…That said, designing a hardware accelerator for AES that can provide high throughput without large overheads in terms of area and power consumption can be a challenging task. Area-efficient AES accelerators that provide high throughput are highly sought-after intellectual property (IP) blocks for resource-constrained environments (e.g., in embedded systems [21]).…”

Section: B Related Workmentioning

confidence: 99%

IMCRYPTO: An In-Memory Computing Fabric for AES Encryption and Decryption

Reis¹,

Geng²,

Niemier³

et al. 2021

Preprint

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This paper proposes IMCRYPTO, an in-memory computing (IMC) fabric for accelerating AES encryption and decryption. IMCRYPTO employs a unified structure to implement encryption and decryption in a single hardware architecture, with combined (Inv)SubBytes and (Inv)MixColumns steps. Because of this step-combination, as well as the high parallelism achieved by multiple units of random-access memory (RAM) and random-access/content-addressable memory (RA/CAM) arrays, IMCRYPTO achieves high throughput encryption and decryption without sacrificing area and power consumption. Additionally, due to the integration of a RISC-V core, IMCRYPTO offers programmability and flexibility. IMCRYPTO improves the throughput per area by a minimum (maximum) of 3.3× (223.1×) when compared to previous ASICs/IMC architectures for AES-128 encryption. Projections show added benefit from emerging technologies of up to 5.3× to the area-delay-power product of IMCRYPTO.

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“…Cipher block will take plaintext with size 128-bit, 192-bit and 256-bit [38], [47]. Key for encrypting and decrypting is depicted as square matrix of bytes [48], [49]. The algorithm supports 128-bit block and 128-bit key, 192-bit key and 256-bit key.…”

Section: F Aes Alogrithmmentioning

confidence: 99%

A Systematic Literature Review Method On AES Algorithm for Data Sharing Encryption On Cloud Computing

Hidayat

Mahardiko

2020

Int. J. Artif. Intell. Res

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Cloud computing is one revolution in information technology (IT) that can share resources, services and data through a network among users. Because users have same rights on the network to transfer data, data are vulnerable to be attacked by unauthorized person. Lately, data security in a system only concentrates on data storage on cloud by utilizing internet security, but a little concentration is found during data transfer. By considering security as a serious problem, an encryption-based proposed system is presented to secure during data transfer. Authors propose an approach to boost system security during data transfer in order to prevent data theft by unauthorized person. To prevent an attack by unauthorized person, Advanced Encryption Standard (AES) will be proposed to secure data transfer and storage in cloud computing. For better future, authors will propose Systematic Literature Review (SLR) to generate suggestions and opportunities in AES cloud computing.

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An enhanced AES algorithm using cascading method on 400 bits key size used in enhancing the safety of next generation internet of things (IOT)

Cited by 13 publications

References 1 publication

Real-time FPGA implementation of concatenated AES and IDEA cryptography system

Real-time FPGA implementation of concatenated AES and IDEA cryptography system

IMCRYPTO: An In-Memory Computing Fabric for AES Encryption and Decryption

A Systematic Literature Review Method On AES Algorithm for Data Sharing Encryption On Cloud Computing

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