An engineering approach to formal digital system design

Larsson, Mats

doi:10.1007/3-540-58450-1_50

Cited by 10 publications

(3 citation statements)

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“…Yet, most formal synthesis approaches deal only with lower levels of abstraction (RT-and gate level) [11] or are restricted to acyclic data flow descriptions at the algorithmic level [8]. Also, they often cover only parts of the synthesis process, e. g. , the scheduling [12].…”

Section: Introductionmentioning

confidence: 99%

Automatic correct scheduling of control flow intensive behavioral descriptions in formal synthesis

Kapp

Sabelfeld

2004

Proceedings of the 41st Annual Design Automation Conference

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Formal synthesis ensures the correctness of hardware synthesis by automatically deriving the circuit implementation by behavior preserving transformations within a theorem prover.In this paper, we present a new approach to formal synthesis that is able to handle control flow intensive descriptions. In particular, we consider here the scheduling phase, which is a central task in high-level synthesis. We describe a methodology employing a new control flow oriented representation which allows the fully automatic scheduling of control flow intensive descriptions in formal synthesis. To obtain scheduled circuits of high quality, the scheduling is guided by conventional scheduling algorithms.

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Section: Introductionmentioning

confidence: 99%

Automatic correct scheduling of control flow intensive behavioral descriptions in formal synthesis

Kapp

Sabelfeld

2004

Proceedings of the 41st Annual Design Automation Conference

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“…Existing approaches in the area of formal synthesis deal with lower levels of abstraction (register-transfer (RT) level, gate level) [8,9,6,10,11] or with pure dataflow graphs at the algorithmic level [12]. This paper addresses formal synthesis at the algorithmic level.…”

Section: Introductionmentioning

confidence: 99%

Formal Synthesis at the Algorithmic Level

Blumenröhr

Sabelfeld

1999

Lecture Notes in Computer Science

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Abstract. In our terminology, the term "formal synthesis" stands for a synthesis process where the implementation is derived from the specification by applying elementary mathematical rules within a theorem prover. As a result the implementation is guaranteed to be correct. In this paper we introduce a new methodology to formally derive register-transfer structures from descriptions at the algorithmic level via program transformations. Some experimental results at the end of the paper show how the run-time complexity of the synthesis process in our approach could be.

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“…[Busc92] and [BaFr96] present reimplementations of the Veritas formal synthesis approach for different theorem provers (LAMBDA and ISABELLE, respectively). Other research activities have been started by [GrMT94], [Wang92] or [Lars95]. They all have one thing in common: they are based on some calculus, i.e.…”

Section: Introductionmentioning

confidence: 99%