An Energy-Oriented Evaluation of Buffer Cache Algorithms Using Parallel I/O Workloads

Power consumption is an increasingly impressing concern for data servers as it directly affects running costs and system reliability. Prior studies have shown most memory space on data servers are used for buffer caching and thus cache replacement becomes critical. Temporally concentrating memory accesses to a smaller set of memory chips increases the chances of free riding through DMA overlapping and also enlarges the opportunities for other ranks to power down. This paper proposes a power and thermal-aware buffer cache replacement algorithm. It conjectures that the memory rank that holds the most amount of cold blocks are very likely to be accessed in the near future. Choosing the victim block from this rank can help reduce the number of memory ranks that are active simultaneously. We use three real-world I/O server traces, including TPC-C, LM-TBF and MSN-BEFS to evaluate our algorithm. Experimental results show that our algorithm can save up to 27% energy than LRU and reduce the temperature of memory up to 5.45 o C with little or no performance degradation.

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Energy Efficient Buffer Cache Replacement for Data Servers

Yue

Zhu

Cai

et al. 2011

2011 IEEE Sixth International Conference on Networking, Architecture, and Storage

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Power consumption is an increasingly impressing concern for data servers as it directly affects running costs and system reliability. Prior studies have shown that most memory space on data servers is used for buffer caching and thus cache replacement becomes critical. Two conflicting factors of buffer caching impacts memory energy efficiency: (1) a higher hit rate reduces memory traffic and thus saves energy; (2) temporally concentrating memory accesses to a smaller set of memory chips increases the chances of "free riding" through DMA overlapping and also makes more memory chips have opportunities to power down. This paper investigates the tradeoff between these two interacting, sometimes conflicting factors and proposes three energy-aware buffer cache replacement algorithms: On a cache miss for a new block b in a file f , evict an victim block from (1) the most recently accessed memory chip; (2) the memory chip that is accessed most recently by file f ; or (3) the memory chip that is accessed most recently by file f and whose last access block belongs to the same hot or cold categories as block b. Simulation results based on three real-world I/O traces, including TPC-R, MSN-BEFS and Exchange, show that our algorithmscan save up to 24.9% energy with marginal degradation in hit rates. Our algorithms show degradation in response time in some experiments. We propose an off-line energy suboptimal replacement algorithm that serves as a theortical reference .

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An Energy-Oriented Evaluation of Buffer Cache Algorithms Using Parallel I/O Workloads

Cited by 4 publications

References 38 publications

PAM: an efficient power-aware multilevel cache policy to reduce energy consumption of storage systems

PAM: an efficient power-aware multilevel cache policy to reduce energy consumption of storage systems

Energy and thermal aware buffer cache replacement algorithm

Energy Efficient Buffer Cache Replacement for Data Servers

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