An Energy-Efficient Virtual Channel Power-Gating Mechanism for On-Chip Networks

Mirhosseini, Amirhossein; Sadrosadati, Mohammad; Fakhrzadehgan, Ali; Modarressi, Mehdi; Azad, Hamid Sarbazi

doi:10.7873/date.2015.0472

Cited by 19 publications

(10 citation statements)

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“…This wake-up process demands both time (T wake_up ) and energy (E wake_up ), which, if not handled timely at the right voltage, imposes a significant overhead on performance and power [2,34,88,103]. Peek-ahead techniques have been proposed in the past to alleviate the performance overhead of sleep modes and issue the wake-up command of a unit in advance [2,4]. Reducing the energy overhead depends on the ability to keep the unit in sleep mode for a long enough time (T br eak_even ) so that the energy savings from the sleep mode can break even with the energy overhead of the wake-up process [2,4,34].…”

Section: Static Power Reduction Techniquesmentioning

confidence: 99%

Itap

Sadrosadati

Ehsani

Falahati³

et al. 2019

ACM Trans. Archit. Code Optim.

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Graphics Processing Units (GPUs) are widely used as the accelerator of choice for applications with massively data-parallel tasks. However, recent studies show that GPUs suffer heavily from resource underutilization, which, combined with their large static power consumption, imposes a significant power overhead. One of the most power-hungry components of a GPU-the execution units-frequently experience idleness when (1) an underutilized warp is issued to the execution units, leading to partial lane idleness, and (2) there is no active warp to be issued for the execution due to warp stalls (e.g., waiting for memory access and synchronization). Although large in total, the idle time of execution units actually comes from short but frequent stalls, leaving little potential for common power saving techniques, such as power-gating. In this article, we propose ITAP, a novel idle-time-aware power management technique, which aims to effectively reduce the static energy consumption of GPU execution units. By taking advantage of different power management techniques (i.e., power-gating and different levels of voltage scaling), ITAP employs three static power reduction modes with different overheads and capabilities of static power reduction. ITAP estimates the idle period length of execution units using prediction and peek-ahead techniques in a synergistic way and then applies the most appropriate static power reduction mode based on the estimated idle period M. Sadrosadati performed part of this work at ETH Zürich. L. Orosa was supported by FAPESP fellowship 2016/18929-4.

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Section: Static Power Reduction Techniquesmentioning

confidence: 99%

Itap

Sadrosadati

Ehsani

Falahati³

et al. 2019

ACM Trans. Archit. Code Optim.

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“…Since the switching activity is given through the communication and the load capacitance is set by the used technology we can only minimize either the frequency or the voltage. These methods are made up of Power Gating, Power Scaling, Clock Gating and, Clock Scaling [7], [12]. Power gating adds sleep transistors to the design to separate a circuit's power supply.…”

Section: Background a Methodologies For Power Savingmentioning

confidence: 99%

“…In contrast, our approach can achieve the same results without additional resources. Compared to the network described in [7] our VC power gating technique covers BE and GS communication and is also capable of switching off complete routers. In case of guaranteed service (GS) connection, the utilization can be zero, but switching off a router is not possible since latency guarantees can be violated otherwise.…”

Section: Power Analysismentioning

confidence: 99%

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Network on Chip Router with Power Management Unit for Improved Network Fabric Power Efficiency

2017

IJRTER

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Abstract-Growing chip integration density and increasing frequencies lead to tremendous leakage power and henceforth to chip heat problems. Power management is one possibility to reduce the power consumption and get the temperature problem under control. Current technology mainly focuses on power-gating techniques on basis of multi-core systems but leaving the network perspective out of scope. We provide a holistic concept, bringing together voltage and frequency scaling techniques for network-on-chips. Following this, network static power consumption could be minimized without affecting the system performance. We present a light-weight power management controller for network-on-chips with online monitoring to optimize the power consumption of network resources. Our work comprises a hardware simulation model for design space exploration of varying technology specific parameters and an FPGA based prototype for verification. The power saving poten-tial heavily depend on the network communication load.

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“…The reduction of static power is always linked with power-or clock-gating mechanisms or DVFS methods and is ©IJRASET (UGC Approved Journal): All Rights are Reserved described in the following section. A general overview of low power designs is given in [6].In [7] a power-gating scheme for virtual channels in on-chip networks is described, which uses an adaptive method to dynamically adjust the number of active VCs based on the on-chip traffic characteristics. But the proposed method does not comprise guaranteed service connection within the network.…”

Section: Related Workmentioning

confidence: 99%

Noc Router With Dedicated Power Management Unit

Khanooni¹

2017

IJRASET

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Growing chip integration density and increasing frequencies lead to tremendous leakage power and henceforth to chip heat problems. Power management is one possibility to reduce the power consumption and get the temperature problem under control. Current technology mainly focuses on power-gating techniques on basis of multi-core systems but leaving the network perspective out of scope. We provide a holistic concept, bringing together voltage and frequency scaling techniques for networkon-chips. Following this, network static power consumption could be minimized without affecting the system performance. We present a light-weight power manages-ment controller for network-on-chips with online monitoring to optimize the power consumption of network resources. Our work comprises a hardware simulation model for design space exploration of varying technology specific parameters and an FPGA based prototype for verification. The power saving potent-tial heavily depend on the network communication load. Keywords-network-on-chip, router, power management, voltage scaling, frequency scaling, clock gating, power gating I.INTRODUCTION Network-on-chips (NoCs) provide a scalable communication infrastructure for architectures with huge numbers of process-ing elements. To preclude that communication becomes the bottleneck in large multiprocessor designs, powerful network routers with large throughput are necessary. Consequently the proportion of network resources of the overall resource consumption is not negligible any longer. Since the start of CPU development, processor frequency increased from few Megahertz to around three Gigahertz. However, in the last few years, core frequency growth has slowed. One of the reasons is a highly significant heat emission which comes in conjunction with increasing frequencies. Chip temperature can increase so much that it could cause actual physical damage to the chip. Because of the tremendous generated heat, simple cooling mechanisms are no longer strong enough to carry away the heat. To prevent the hardware from destruction, hardware monitors are included in the chips and switch off the device before it comes to actual damage. For taking corrective actions even before the heat increases too much, dynamic voltage and frequency scaling (DVFS) methods are applied [1]. The majority of DVFS methods focuses on the processor perspective and the communication is not considered. However, there are first developments to extend these methods also to the network layer [2], [3], [4].With shrinking technology sizes, especially beyond 90nm, the amount of static power dissipation reaches a critical proportion of the total power. Accessory, the increasing static power dissipation causes high temperatures even in idle cir-cutis and hence the static leakage is not negligible any more. The rising complexity of on-chip communication structures, is reaching a state where dedicated power management becomes beneficial. Moreover, with increasing network sizes it will not be possible to have one globally sy...

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An Energy-Efficient Virtual Channel Power-Gating Mechanism for On-Chip Networks

Cited by 19 publications

References 0 publications

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Network on Chip Router with Power Management Unit for Improved Network Fabric Power Efficiency

Noc Router With Dedicated Power Management Unit

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