An Energy-Efficient Mixed-Bitwidth Systolic Accelerator for NAS-Optimized Deep Neural Networks

Mao, Wei; Dai, Liuyao; Li, Kai; Cheng, Quan; Wang, Yuhang; Du, Laimin; Luo, Shaobo; Huang, Mingqiang; Yu, Hao

doi:10.1109/tvlsi.2022.3210069

Cited by 6 publications

(2 citation statements)

References 27 publications

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“…Besides, the input is vectorized rather than scalar. Compared with classical systolic array, vector systolic dataflow can reduce processing time and improve accelerator energy efficiency [28], [29]. In this paper, we also adopt the accelerator architecture of this vector systolic array, which is optimized further by employing the proposed approximate multiplier.…”

Section: Systolic Arraymentioning

confidence: 99%

“…Vector systolic array is a novel architecture of neural network accelerator. It combines the characteristics of systolic array and parallel broadcast structure, which effectively improves energy efficiency by using data reuse and reducing data drive power [27], [28], [29]. On this basis, an approximate vector systolic array is proposed, as shown in Figure 1.…”

Section: A Architecture Of Proposed Acceleratormentioning

confidence: 99%

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A Low-Power DNN Accelerator With Mean-Error-Minimized Approximate Signed Multiplier

Du,

Ni,

Liu

et al. 2024

IEEE Open J. Circuits Syst.

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Approximate computing is an emerging and effective method for reducing energy consumption in digital circuits, which is critical for energy-efficient performance improvement of edge-computing devices. In this paper, we propose a low-power DNN accelerator with novel signed approximate multiplier based on probability-optimized compressor and error compensation. The probability-optimized compressor is customized for partial product matrix (PPM) of signed operands, which gets the optimal logic circuit after probabilistic analysis and optimization. At the same time, we explored the PPM truncation method, found out the impact of different partial product (PP) truncation numbers on circuit benefit and error, and achieved a more ideal performance-error tradeoff through a reasonable error compensation method. In the optimal case of 8 bits, the proposed approximate multiplier saves 49.84% power, 46.41% area and 24.65% delay compared to the exact multiplier. We employed the proposed approximate multiplier in the vector systolic array as the processing element (PE). Under the VGG-16 evaluation, the proposed accelerator achieves performance improvement of energy efficiency 1.96×, while the error loss was only 0.95%.

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Section: Systolic Arraymentioning

confidence: 99%