An energy-efficient memory-based high-throughput VLSI architecture for convolutional networks

Kang, Mingu; Gonugondla, Sujan K.; Keel, Min-Sun; Shanbhag, Naresh R.

doi:10.1109/icassp.2015.7178127

Cited by 33 publications

(29 citation statements)

References 5 publications

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“…Setting c = MPC yields MPC (dB) = 10 log 10 ( MPC ) 2 indicating that c is a decreasing function of MPC . Thus, (14) has the same form as (1) with an additional (last term) clipping noise factor.…”

Section: The Minimum Precision Criterion (Mpc)mentioning

confidence: 99%

Fundamental limits on the precision of in-memory architectures

Gonugondla

Sakr

Dbouk

et al. 2020

Proceedings of the 39th International Conference on Computer-Aided Design

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Section: The Minimum Precision Criterion (Mpc)mentioning

confidence: 99%

Fundamental limits on the precision of in-memory architectures

Gonugondla

Sakr

Dbouk

et al. 2020

Proceedings of the 39th International Conference on Computer-Aided Design

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“…To enable sparse distributed memory, compute memory has been proposed as a viable implementation architecture [46]. Compute memory [44], [45] is an in-memory processing architecture that implements both memory and processing in a single architecture in order to completely eliminate the processor-memory interface. The compute memory architecture implements inference algorithms in the periphery of the memory array, and does not modify the core bit-cell array, thus maintaining the storage density.…”

Section: Secure Microarchitecturesmentioning

confidence: 99%

Microprocessor Optimizations for the Internet of Things: A Survey

Adegbija

Rogacs

Patel

et al. 2018

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-The Internet of Things (IoT) refers to a pervasive presence of interconnected and uniquely identifiable physical devices. These devices' goal is to gather data and drive actions in order to improve productivity, and ultimately reduce or eliminate reliance on human intervention for data acquisition, interpretation and use. The proliferation of these connected low-power devices will result in a data explosion that will significantly increase data transmission costs with respect to energy consumption and latency. Edge computing reduces these costs by performing computations at the edge nodes, prior to data transmission, to interpret and/or utilize the data. While much research has focused on the IoT's connected nature and communication challenges, the challenges of IoT embedded computing with respect to device microprocessors has received much less attention. This article explores IoT applications' execution characteristics from a microarchitectural perspective and the microarchitectural characteristics that will enable efficient and effective edge computing. To tractably represent a wide variety of next-generation IoT applications, we present a broad IoT application classification methodology based on application functions, to enable quicker workload characterizations for IoT microprocessors. We then survey and discuss potential microarchitectural optimizations and computing paradigms that will enable the design of right-provisioned microprocessors that are efficient, configurable, extensible, and scalable. Our work provides a foundation for the analysis and design of a diverse set of microprocessor architectures for next-generation IoT devices.

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“…Recently, we proposed Compute Memory (CM) [2], [3] an inmemory computing architecture, where both computation and storage are implemented in a low swing/low signal-to-noise ratio (SNR) domain thereby eliminating the processor-memory interface completely, and providing a 5.0 × energy reduction and 4.9 × throughput enhancement for pattern recognition application in a 45 nm CMOS process. CM preserves the storage density, the conventional SRAM's read/write functionality, and is well-suited for inference kernels such as SDM which can compensate for non-deterministic hardware operations.…”

Section: Introductionmentioning

confidence: 99%

In-Memory Computing Architectures for Sparse Distributed Memory

Kang

Shanbhag

2016

IEEE Trans. Biomed. Circuits Syst.

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This paper presents an energy-efficient and high-throughput architecture for Sparse Distributed Memory (SDM)-a computational model of the human brain [1]. The proposed SDM architecture is based on the recently proposed in-memory computing kernel for machine learning applications called Compute Memory (CM) [2], [3]. CM achieves energy and throughput efficiencies by deeply embedding computation into the memory array. SDM-specific techniques such as hierarchical binary decision (HBD) are employed to reduce the delay and energy further. The CM-based SDM (CM-SDM) is a mixed-signal circuit, and hence circuit-aware behavioral, energy, and delay models in a 65 nm CMOS process are developed in order to predict system performance of SDM architectures in the auto- and hetero-associative modes. The delay and energy models indicate that CM-SDM, in general, can achieve up to 25 × and 12 × delay and energy reduction, respectively, over conventional SDM. When classifying 16 × 16 binary images with high noise levels (input bad pixel ratios: 15%-25%) into nine classes, all SDM architectures are able to generate output bad pixel ratios (Bo) ≤ 2%. The CM-SDM exhibits negligible loss in accuracy, i.e., its Bo degradation is within 0.4% as compared to that of the conventional SDM.

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An energy-efficient memory-based high-throughput VLSI architecture for convolutional networks

Cited by 33 publications

References 5 publications

Fundamental limits on the precision of in-memory architectures

Fundamental limits on the precision of in-memory architectures

Microprocessor Optimizations for the Internet of Things: A Survey

In-Memory Computing Architectures for Sparse Distributed Memory

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