An Energy-Efficient Dual-Field Elliptic Curve Cryptography Processor for Internet of Things Applications

Yeh, Ling-Yu; Chen, Po‐Jen; Pai, Chen-Chun; Liu, Tsung-Te

doi:10.1109/tcsii.2020.3012448

Cited by 28 publications

(23 citation statements)

References 15 publications

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“…The area of this design is the smallest in Table 3 designs. In terms of the area‐time (AT), this design is also at least 600% and 68% superior to lightweight designs [1, 4, 5] and high‐speed designs [6, 7], respectively. In terms of power consumption, although our power consumption is higher than other designs, due to the shorter computation time of our design, the energy is lower than other designs [1, 4, 5].…”

Section: A Speed‐area‐efficient Hardware Ecpm‐enginementioning

confidence: 99%

A speed‐area‐efficient hardware ECPM‐engine in GF(p) over generic Weierstrass curves

Xie,

He,

Liu

et al. 2024

Electronics Letters

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This paper proposes a 256‐bit speed‐area‐efficient hardware elliptic curve point‐multiplication engine (ECPM‐engine) in GF(p) over generic Weierstrass curves, which is optimized by a new speed‐area‐efficient radix‐64 Montgomery modular multiplication (R64MMM) and a novel Montgomery ladder scheduling. The R64MMM calls one 129‐bit adder and one (64x64+129)‐bit multiply‐accumulator (64‐129‐MAC) in parallel to make a trade‐off between speed and area. The novel Montgomery ladder scheduling is used to improve the utilization of MAC in ECPM operation. In this ECPM‐engine, both MAC utilization in R64MMM operations and R64MMM utilization in ECPM operations are close to 100%. The result shows that the proposed ECPM‐engine consumes 72k gates when the clock frequency is 714 MHz with a 90 nm standard cell library, and it computes one 256‐bit ECPM in 0.14 ms.

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Section: A Speed‐area‐efficient Hardware Ecpm‐enginementioning

confidence: 99%

A speed‐area‐efficient hardware ECPM‐engine in GF(p) over generic Weierstrass curves

Xie,

He,

Liu

et al. 2024

Electronics Letters

View full text Add to dashboard Cite

show abstract

“…Its widely adoption is due to its ability to provide a similar security level with relatively smaller key-sizes as compared to the current public-key security standard (i.e., the Rivest-Shammir-Adleman (RSA) algorithm) [2]. From structural point of view, ECC involves four layers of operations [3]. The top most layer (fourth layer) ensures the encryption and decryption of data.…”

Section: Introductionmentioning

confidence: 99%

“…In addition to the layer model of ECC, there are two coordinate systems, i.e., affine, and projective. In past, the latter has more frequently been employed to optimize throughput [3]. Furthermore, two field representations, i.e., prime (GF(P)) and binary (GF(2 m )), are commonly involved.…”

Section: Introductionmentioning

confidence: 99%

“…Furthermore, two field representations, i.e., prime (GF(P)) and binary (GF(2 m )), are commonly involved. The prime field representation is generally utilized for software-based implementations while the binary field representation is preferred for hardware deployments [3,4].…”

Section: Introductionmentioning

confidence: 99%

“…Concerning the security strength of ECC, several implementation models such as Weierstrass [3,4], Binary-edward (BEC) [5], Hessian (HC) [6], and Binary-huff (BHC) [7] are frequently utilized. The fundamental model (Weierstrass) in ECC allows access to attackers and, therefore, exposes the secret-key via simple power attacks (SPA) [5][6][7].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

AREEBA: An Area Efficient Binary Huff-Curve Architecture

et al. 2021

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Elliptic curve cryptography is the most widely employed class of asymmetric cryptography algorithm. However, it is exposed to simple power analysis attacks due to the lack of unifiedness over point doubling and addition operations. The unified crypto systems such as Binary Edward, Hessian and Huff curves provide resistance against power analysis attacks. Furthermore, Huff curves are more secure than Edward and Hessian curves but require more computational resources. Therefore, this article has provided a low area hardware architecture for point multiplication computation of Binary Huff curves over GF(2163) and GF(2233). To achieve this, a segmented least significant digit multiplier for polynomial multiplications is proposed. In order to provide a realistic and reasonable comparison with state of the art solutions, the proposed architecture is modeled in Verilog and synthesized for different field programmable gate arrays. For Virtex-4, Virtex-5, Virtex-6, and Virtex-7 devices, the utilized hardware resources in terms of hardware slices over GF(2163) are 5302, 2412, 2982 and 3508, respectively. The corresponding achieved values over GF(2233) are 11,557, 10,065, 4370 and 4261, respectively. The reported low area values provide the acceptability of this work in area-constrained applications.

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Novel Experimental Prototype for Determining Malicious Degree in Vulnerable Environment of Internet-of-Things

Anil

2022

Cybernetics Perspectives in Systems

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An Energy-Efficient Dual-Field Elliptic Curve Cryptography Processor for Internet of Things Applications

Cited by 28 publications

References 15 publications

A speed‐area‐efficient hardware ECPM‐engine in GF(p) over generic Weierstrass curves

A speed‐area‐efficient hardware ECPM‐engine in GF(p) over generic Weierstrass curves

AREEBA: An Area Efficient Binary Huff-Curve Architecture

Novel Experimental Prototype for Determining Malicious Degree in Vulnerable Environment of Internet-of-Things

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