An Energy-Efficient Deep Convolutional Neural Network Accelerator Featuring Conditional Computing and Low External Memory Access

Kim, Minkyu; Seo, Jae-sun

doi:10.1109/jssc.2020.3029235

Cited by 13 publications

(9 citation statements)

References 27 publications

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“…[119] proposes a similar strategy, but the sign estimation is done either after representing weights in ternary format, or after using a sign function, which simplifies the computations, while maintaining the prediction accuracy. Minkyu Kim et al [61] exploits the max-pooling layers and adopts a precision-cascading scheme to predict and calculate only the maximum value of a convolution operation. This technique, combined with a zero-skipping scheme, can efficiently avoid redundant computations without affecting neuron synapses that contribute a lot in classification accuracy.…”

Section: Skippingmentioning

confidence: 99%

“…With respect to the employed precision, the Skipping approximation techniques mainly use high precision (i.e., 16-bit and 32-bit precision). However, [61] and [94] use lower precision, i.e., 12-bit and 8-bit respectively. Again, when considering simpler evaluation cases (e.g., LeNet, MNIST, and/or 32-bit precision) Skipping approximation delivers minimal accuracy loss and very high energy gains.…”

Section: Performance Analysismentioning

confidence: 99%

“…For example, [48] achieved 24% energy reduction and 1.43% accuracy loss on VGG-16 while the respective values are 15% and 2.7% when considering MobileNet. Notably, with 12-bit precision, [61] features 1.7x better energy efficiency (TOPS/W) and only 0.8% accuracy loss for VGG-16 on the ImageNet dataset.…”

Section: Performance Analysismentioning

confidence: 99%

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Hardware Approximate Techniques for Deep Neural Network Accelerators: A Survey

et al. 2022

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Deep Neural Networks (DNNs) are very popular because of their high performance in various cognitive tasks in Machine Learning (ML). Recent advancements in DNNs have brought beyond human accuracy in many tasks, but at the cost of high computational complexity. To enable efficient execution of DNN inference, more and more research works, therefore, exploit the inherent error resilience of DNNs and employ Approximate Computing (AC) principles to address the elevated energy demands of DNN accelerators. This article provides a comprehensive survey and analysis of hardware approximation techniques for DNN accelerators. First, we analyze the state of the art and by identifying approximation families, we cluster the respective works with respect to the approximation type. Next, we analyze the complexity of the performed evaluations (with respect to the dataset and DNN size) to assess the efficiency, the potential, and limitations of approximate DNN accelerators. Moreover, a broad discussion is provided, regarding error metrics that are more suitable for designing approximate units for DNN accelerators as well as accuracy recovery approaches that are tailored to DNN inference. Finally, we present how Approximate Computing for DNN accelerators can go beyond energy efficiency and address reliability and security issues, as well.

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Section: Skippingmentioning

confidence: 99%

Section: Performance Analysismentioning

confidence: 99%

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Hardware Approximate Techniques for Deep Neural Network Accelerators: A Survey

et al. 2022

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“…Many energy-efficient hardware accelerators have been proposed to reduce power consumption and improve the speed of DCNN computing in recent years. These accelera-tors based on application-specific integrated circuits (ASIC) [7,8,9,10,11,12,13,14,15,16,17,18,19] and fieldprogrammable gate array (FPGA) [20,21,22,23,24,25,26] have achieved low latency and high efficiency on CNN computing. Two classic CNN of AlexNet and VGG have been demonstrated the excellent performance earlier, including UNPU [7], DSIP [12], Eyeriss [13], and DNPU [18].…”

Section: Introductionmentioning

confidence: 99%

“…Two classic CNN of AlexNet and VGG have been demonstrated the excellent performance earlier, including UNPU [7], DSIP [12], Eyeriss [13], and DNPU [18]. Moreover, some works exploited the accelerators performance by reducing off-chip memory access [8,27,28].…”

Section: Introductionmentioning

confidence: 99%

CASSANN-v2: A high-performance CNN accelerator architecture with on-chip memory self-adaptive tuning

Liu

Qiao

Chen

et al. 2022

IEICE Electron. Express

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This work proposes a high-performance reconfigurable CNN accelerator architecture, called CASSANN-v2, which can achieve 1TOPS peak performance at 1 GHz. CASSANN-v2 provides the function of onchip SRAM memory real-time adaptive tuning by parameter configuration to reduce the intermediate output data transmission to further exploit the acceleration performance. The system simulation results show that CASSANN-v2 exhibits excellent performance on VGG-16 and ResNet-18 inference, with a throughput of 1009.54GOPS and 923.24GOPS at 1 GHz, which achieved 98.59% and 90.20% average processing element utilization, respectively. Compared with state-of-the-art accelerator works, CASSANN-v2 improves the resource utilization by 2.02× in

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Energy-Efficient Duty-Cycle Hybrid Medium Access Control Protocol for Wireless Sensor Network

Tolani

Bajpai

Balodi

et al. 2023

Wireless Pers Commun

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This work proposes an energy-efficient duty-cyclebased hybrid medium access control protocol. The proposed protocol optimally adjusts the turn-on and off time of the trans-receiver radio to save energy consumption. Both cluster head and sensing devices save energy by estimating the utilization of slots. In reserved slot duration, each sensor device checks its buffer status in a regular interval and turns off its radio when the buffer becomes empty. Each sensor device transmits a slot utilization status to the cluster head device. Cluster head device also turn-on and off its radio based on slot utilization status of sensing devices. A duty cycle approach is proposed for optimal energy consumption. The proposed protocol uses less energy than existing equivalent protocols, according to the mathematical and simulation results. For simulation study, the network is analysed for low, medium, and high data traffic conditions. Simulation results depict, exactly similar results of analytical and mathematical analysis prove the validity of the work.

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An Energy-Efficient Deep Convolutional Neural Network Accelerator Featuring Conditional Computing and Low External Memory Access

Cited by 13 publications

References 27 publications

Hardware Approximate Techniques for Deep Neural Network Accelerators: A Survey

Hardware Approximate Techniques for Deep Neural Network Accelerators: A Survey

CASSANN-v2: A high-performance CNN accelerator architecture with on-chip memory self-adaptive tuning

Energy-Efficient Duty-Cycle Hybrid Medium Access Control Protocol for Wireless Sensor Network

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