An Energy-Efficient Cache Architecture for Chip-Multiprocessors Based on Non-Uniformity Accesses

Safayenikoo, Pooneh; Asad, Arghavan; Mohammadi, Fazel

doi:10.1109/ccece.2018.8447736

Cited by 3 publications

(5 citation statements)

References 10 publications

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“…Table 1 gives the average normalized interconnection cost of GBI compared to fully reduced multiple bus system [10]. We notice a reduction of about 30 % in cost across the number of cores from 16…”

Section: Geometrical Bus Interconnection (Gbi) [12] Costmentioning

confidence: 99%

“…In addition, our proposed cache system solution may also provide the ability to increase the cache levels and sizes within the cache hierarchy upon cache reconfiguration in order to optimize the system for cost, performance and power consumption. Some earlier research [13]- [16] have addressed various cache system architecture, issues and solutions for improved performance. In [13], the authors addressed analyzing memory performance for tiled many-core CMP.…”

Section: Introductionmentioning

confidence: 99%

“…Charles et al [15] looked at cache reconfiguration for network-on-chip (NoC) based many-core CMP. Safayenikoo et al [16] suggested an energy-efficient cache architecture to address the problem of increased leakage power resulting from large area of LLC (as much as 50% of the chip area) due to its increased size. Most of the work reported in [13]- [16] may require complex cache design process.…”

Section: Introductionmentioning

confidence: 99%

“…Safayenikoo et al [16] suggested an energy-efficient cache architecture to address the problem of increased leakage power resulting from large area of LLC (as much as 50% of the chip area) due to its increased size. Most of the work reported in [13]- [16] may require complex cache design process. Our proposed cache system solution is simple and do not add any extra or difficult cache design process.…”

Section: Introductionmentioning

confidence: 99%

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An efficient multi-level cache system for geometrically interconnected many-core chip multiprocessor

Ramesh

Abed

2022

IJRES

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<p><span lang="EN-US">Many-core chip multiprocessor offers high parallel processing power for big data analytics; however, they require efficient multi-level cache and interconnection to achieve high system throughput. Using on-chip first level L1 and second level L2 per core fast private caches is expensive for large number of cores. In this paper, for moderate number of cores from 16 to 64, we present a cost and performance efficient multi-level cache system with per core L1 and last level shared bus cache on each bus line of a cost-efficient geometrically bus-based interconnection. In our approach, we extracted cache hit and miss concurrencies and applied concurrent average memory access time to more accurately determine the cache system performance. We conducted least recently used cache policy-based simulation for cache system with L1, with L1/L2, and with L1/shared bus cache. Our simulation results show that an average system throughput improvement of 2.5x can be achieved by using system with L1/shared bus cache system compared to using only first level L1 or L1/L2. Further, we show that the throughput degradation for the proposed cache system is only within 5% for a single bus fault, suggesting a good bus fault tolerance.</span></p>

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Section: Geometrical Bus Interconnection (Gbi) [12] Costmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

An efficient multi-level cache system for geometrically interconnected many-core chip multiprocessor

Ramesh

Abed

2022

IJRES

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“…At the same time, in this paper, we investigate the role of data encoding to reduce power in NoC instead of developing sophisticated router architectures. The data encoding scheme is another method that was employed to reduce the link power dissipation [33] [34] [45][46][47][48]. NoΔ compression [35] was proposed to reduce traffic in Network on Chip and save energy by lowering the network load.…”

Section: Related Workmentioning

confidence: 99%

An energy efficient non-uniform Last Level Cache Architecture in 3D chip-multiprocessors

Safayenikoo

Asad

Mohammadi

2017

2017 18th International Symposium on Quality Electronic Design (ISQED)

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With technology scaling, the size of cache systems in chip-multiprocessors (CMPs) has been dramatically increased to efficiently store and manipulate a large amount of data in future applications and decrease the gap between cores and off-chip memory accesses. For future CMPs architecting, 3D stacking of LLCs has been recently introduced as a new methodology to combat to performance challenges of 2D integration and the memory wall. However, the 3D design of SRAM LLCs has made the thermal problem even more severe. It, therefore, incurs more leakage energy consumption than conventional SRAM cache architectures in 2Ds due to dense integration. In this paper, we propose two different architectures that exploit the data compression to reduce the energy of LLC and interconnects in 3D-ICs. The fundamental idea of the proposed architectures is to use the non-uniform distribution of the accesses, invalid lines, zero-value lines, and frequent-value (FV) lines in banks of an LLC for decreasing both dynamic and leakage energy. The proposed architectures based on nonuniform cache architectures (NUCA) disable cache banks with low accesses and high invalid, zero, and FV lines, leading to high energy efficiency.

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Improving Effectiveness of Parallel Processing with Smart Cache Utilization for Energy Saving and Temperature Reduction In Chip Multiprocessors

Kulkarni

Mahajan

2022

2022 IEEE 4th International Conference on Cybernetics, Cognition and Machine Learning Applications (ICCCMLA)

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An Energy-Efficient Cache Architecture for Chip-Multiprocessors Based on Non-Uniformity Accesses

Cited by 3 publications

References 10 publications

An efficient multi-level cache system for geometrically interconnected many-core chip multiprocessor

An efficient multi-level cache system for geometrically interconnected many-core chip multiprocessor

An energy efficient non-uniform Last Level Cache Architecture in 3D chip-multiprocessors

Improving Effectiveness of Parallel Processing with Smart Cache Utilization for Energy Saving and Temperature Reduction In Chip Multiprocessors

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