An Energy-Efficient and Fast Scheme for Hybrid Storage Class Memory in an AIoT Terminal System

Sun, Hao; Chen, Lan; Hao, Xiaoran; Liu, Chenji; Ni, Mao

doi:10.3390/electronics9061013

Cited by 18 publications

(9 citation statements)

References 30 publications

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“…For a comparison purpose, we additionally simulate a scheme that adds a page to DRAM if a write operation on that page occurs first time and page migration between DRAM and NVM is allowed. We call this scheme migration-allowed, which is a typical scheme used in hybrid memory systems [11,17,27,28]. In the experiments, the ratio of DRAM is varied to 10%, 15%, and 20% of the total main memory capacity.…”

Section: Resultsmentioning

confidence: 99%

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Characterization of Android Memory References and Implication to Hybrid Memory Management

Lee

Bahn

2021

IEEE Access

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In this article, we analyze Android applications' memory reference behaviors, and observe that smartphone memory accesses are different from traditional computer systems with respect to the following five aspects. 1) A limited number of hot pages account for a majority of memory writes, and these hot pages have similar logical addresses regardless of application types. 2) The identities of these hot pages are shared library, linker, and stack regions. 3) The memory access behaviors of hot pages do not change significantly as time progresses even after applications finish their launching. 4) The skewness of memory write accesses in Android is extremely stronger than that of desktop systems. 5) In predicting rereference likelihood of hot pages, temporal locality is better than reference frequency. Based on these observations, we present a new smartphone memory management scheme for DRAM-NVM hybrid memory. Adopting NVM is effective in power-saving of smartphones, but NVM has weaknesses in write operations. Thus, we aim to identify write-intensive pages and place them on DRAM. Unlike previous studies, we prevent migration of pages between DRAM and NVM, which eliminates unnecessary NVM write traffic that accounts for 32-42% of total write traffic. By judiciously managing the admission of hot pages in DRAM, our scheme reduces the write traffic to NVM by 42% on average without performance degradations.

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Section: Resultsmentioning

confidence: 99%

“…Sun et al present a hybrid memory management technique for AIoT (Artificial intelligence Internet of Things) systems [28]. Specifically, they reduce the energy consumption and optimize I/O performance of AIoT systems by migrating write-intensive data from NVM to DRAM.…”

Section: B Hybrid Memory Technologiesmentioning

confidence: 99%

Characterization of Android Memory References and Implication to Hybrid Memory Management

Lee

Bahn

2021

IEEE Access

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“…In order to meet the ever-increasing demand for computing power and low power of IoT device, high storage density, near zero leakage power NVM (PCM, STT-RAM, RRAM, etc.) has been studied and tried at different levels from external memory to main memory [15,16,17]. These methods of solve the asymmetry of NVM are very valuable.…”

Section: Related Workmentioning

confidence: 99%

Write-awareness prefetching for non-volatile cache in energy-constrained IoT device

Chen

Hao

et al. 2022

IEICE Electron. Express

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Large-sized cache is beneficial to improve CPU performance especially for IoT applications with huge amount of data. However, largesized SRAM cache also increases chip area and energy which is not friendly to resources limited IoT terminals. The STT-RAM with high storage density and near zero leakage is regarded as an ideal technology to replace SRAM. Prefetching is a vital method to hide the access latency of off-chip memory. Nevertheless, traditional prefetchers for SRAM is inadequate for MRAM cache with read-write asymmetry. Aggressive prefetching for STT-RAM cache would cause cache congestion and dynamic energy rise because of STT-RAM long write latency and high write energy. In response to the above problems, this paper novelty proposes WANCP (Write-awareness Adaptive Non-volatile Cache Prefetch), which adaptively adjusts the prefetch aggressiveness according to the saturation of MSHR (Miss-status Handling Registers) in the L2 cache. Experiments show that, for applications that are sensitive to L2 cache capacity, the CPU performance with STT-RAM L2 cache can be improved by up to 33.2% and 10.9 % on average compared to the same sized SRAM L2 cache. The proposed WANCP can further improve the CPU performance 0.4 % on average, and reduce the prefetch energy by 9.4% on average.

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“…The main page policies of modern DRAM are the open-page policy (OPP) and the close-page policy (CPP) [16,17]. As an example, the access latency of DDR3-1600 memory in OPP and CPP modes are shown in Table 1.…”

Section: Introductionmentioning

confidence: 99%

Memory Access Optimization of a Neural Network Accelerator Based on Memory Controller

Wei

Chen

et al. 2021

Electronics

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Special accelerator architecture has achieved great success in processor architecture, and it is trending in computer architecture development. However, as the memory access pattern of an accelerator is relatively complicated, the memory access performance is relatively poor, limiting the overall performance improvement of hardware accelerators. Moreover, memory controllers for hardware accelerators have been scarcely researched. We consider that a special accelerator memory controller is essential for improving the memory access performance. To this end, we propose a dynamic random access memory (DRAM) memory controller called NNAMC for neural network accelerators, which monitors the memory access stream of an accelerator and transfers it to the optimal address mapping scheme bank based on the memory access characteristics. NNAMC includes a stream access prediction unit (SAPU) that analyzes the type of data stream accessed by the accelerator via hardware, and designs the address mapping for different banks using a bank partitioning model (BPM). The image mapping method and hardware architecture were analyzed in a practical neural network accelerator. In the experiment, NNAMC achieved significantly lower access latency of the hardware accelerator than the competing address mapping schemes, increased the row buffer hit ratio by 13.68% on average (up to 26.17%), reduced the system access latency by 26.3% on average (up to 37.68%), and lowered the hardware cost. In addition, we also confirmed that NNAMC efficiently adapted to different network parameters.

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An Energy-Efficient and Fast Scheme for Hybrid Storage Class Memory in an AIoT Terminal System

Cited by 18 publications

References 30 publications

Characterization of Android Memory References and Implication to Hybrid Memory Management

Characterization of Android Memory References and Implication to Hybrid Memory Management

Write-awareness prefetching for non-volatile cache in energy-constrained IoT device

Memory Access Optimization of a Neural Network Accelerator Based on Memory Controller

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