An endurance-free ferroelectric random access memory as a non-volatile RAM

Selected Advances in Nanoelectronic Devices

“…Many commercial nonvolatile FeRAM memory chips have been already demonstrated exhibiting low operating voltage (<1 V), lowest power consumption, fast random access read/write operations (comparable to that of SRAM), and endurance free memory functioning, however, FeRAM memory products have shown limited memory capacities (< 128 Mb) due to their poor scalability [324], [325]. FeFETs are in principle scalable to the crystal unit-cell size (below 10nm) because the information is stored with an electric polarization in a ferroelectric gate insulator.…”

Future Memory Technology and Ferroelectric Memory as an Ultimate Memory Solution

“…17. Cross-sectional micrographs both (a) in a peripheral circuitry region and (b) in a cell region, (c) in which one of the cell capacitors is pictured (Jung et al, 2008).…”

“…This is, in practice, because repeating the polarization reversal-read and write operation, does not need boost up base voltage unlike flash memory, stemming from balance of read and write energy of the same order of magnitude (Kryder & Kim, 2009). A good example of this is that, according to literature published recently, one of the FRAMs as a non-volatile memory has attractive memory performance such as fast access time of 1.6 GB/sec, negligible stand-by current of less than 10 micro-Ampere, and low voltage operation of less than 2.0 V even in read and write action without erase operation (Shiga et al, 2009;Jung et al, 2008). Since then, there have been tremendous improvements in FRAM developments, migrating from sub-micron to nano scale in technology node.…”

“…In similar to DRAM, an attempt to build smaller unit cell in size was in the late 1990's that one transistor and one capacitor (1T1C) per unit memory was developed (Jung et al, 1998). Since then, many efforts to build high density FRAM have been pursued, leading to several ten mega bits in density during the 2000s Kim et al, 2002;Kang et al, 2006;Hong et al, 2007;Jung et. al, 2008).…”

Proposal of a ferroelectric multi‐bit memory structure for reliable operation at sub‐100 nm scale

“…Polarisation reversal, corresponding to data conversion, arises at low voltages in the sub-μs time scale [3][4][5]. Moreover, endurance and retention performance levels have already met the requirements for commercialisation [6,7]. Regardless of how superior the FeRAM may be, its integration density is insufficient compared with silicon-based flash memory [8].…”