An endurance evaluation method for flash EEPROM

Zous, N.K.; Chen, Yin-Jen; Chin, C.Y.; Tsai, Wen-Jer; Lu, Tsung-Chien; Chen, Ming-Shiang; Lü, Wei; Wang, Tahui; Pan, S.C.; Lu, Chih‐Yuan

doi:10.1109/ted.2004.826871

Cited by 9 publications

(2 citation statements)

References 13 publications

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“…Zous et al [25] proposed a tolerance assessment method that initial P/E window and erase threshold voltage have a linear relation. This linear relation can be used to assess the performance of the tunnel oxide and optimize the erase waveform.…”

Section: B Model-based Techniques For Optimizing Reliability Of Nand Flash Memorymentioning

confidence: 99%

RBER-Aware Lifetime Prediction Scheme for 3D-TLC NAND Flash Memory

Zhang

et al. 2019

IEEE Access

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NAND flash memory is widely used in various computing systems. However, flash blocks can sustain only a limited number of program/erase (P/E) cycles, which are referred to as the endurance. On one hand, in order to ensure data integrity, flash manufacturers often define the maximum P/E cycles of the worst block as the endurance of flash blocks. On the other hand, blocks exhibit large endurance variations, which introduce two serious problems. The first problem is that the error correcting code (ECC) is often over-provisioned, as it has to be designed to tolerate the worst case to ensure data integrity, which causes longer decoding latency. The second problem is the underutilized block's lifespan due to conservatively defined block endurance. Raw bit error rate (RBER) of most blocks have not arrived the allowable RBER based on the nominal endurance point, which implies that the conventional P/E cycle-based block retirement policies may waste large flash storage space. In this paper, to exploit the storage capacity of each flash block, we propose an RBER-aware lifetime prediction scheme based on machine learning technologies. We consider the problem that the model can lose prediction effectiveness over time and use incremental learning to update the model for adapting the changes at different lifetime stages. At run time, trained data will be gradually discarded, which can reduce memory overhead. For evaluating our purpose, four wellknown machine learning techniques have been compared in terms of predictive accuracy and time overhead under our proposed lifetime prediction scheme. We also compared the predicted values with the tested values obtained in the real NAND flash-based test platform, and the experimental results show that the support vector machine (SVM) models based on our proposed lifetime prediction scheme can achieve as high as 95% accuracy for flash blocks. We also apply our proposed lifetime prediction scheme to predict the actual endurance of flash blocks at four different retention times, and the experimental results show that it can significantly improve the maximum P/E cycle of flash blocks from 37.5% to 86.3% on average. Therefore, the proposed lifetime prediction scheme can provide a guide for block endurance prediction.

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Section: B Model-based Techniques For Optimizing Reliability Of Nand Flash Memorymentioning

confidence: 99%

RBER-Aware Lifetime Prediction Scheme for 3D-TLC NAND Flash Memory

Zhang

et al. 2019

IEEE Access

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show abstract

“…The present scheme reliably reproduces P/E stress induced up to cycles, in contrast with the conventional schemes yielding consistently lower values. Generally, the program and erase stress effects have been separately investigated in the reference cell [1], [2]. It is clear from Fig.…”

Section: Introductionmentioning

confidence: 99%

Reliable extraction of cycling induced interface states implementing realistic P/E stresses in reference cell: comparison with flash memory cell

Baek

Kim²,

Son³

et al. 2006

IEEE Electron Device Lett.

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The cycling induced interface states in floating-gate EEPROM cells are reliably extracted by implementing accurate program/erase stresses in the reference cell. The interface states measured directly from the memory cell via charge pumping are shown different from those obtained conventionally from the reference cell. The reasons for these different levels of extraction are elucidated and a new method is presented for accurate determination of interface trap density. The technique is based on introducing the equivalent gate voltage with offset voltage at the reference cell by which to simulate realistically the cycling stresses as occur in the flash memory cell itself.

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An endurance evaluation method for flash EEPROM

Cited by 9 publications

References 13 publications

RBER-Aware Lifetime Prediction Scheme for 3D-TLC NAND Flash Memory

RBER-Aware Lifetime Prediction Scheme for 3D-TLC NAND Flash Memory

Reliable extraction of cycling induced interface states implementing realistic P/E stresses in reference cell: comparison with flash memory cell

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