2015
DOI: 10.1039/c5ra07164j
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An empirical study-based state space model for multilayer overlay errors in the step-scan lithography process

Abstract: In semiconductor manufacturing, the multilayer overlay lithography process is a typical multistage manufacturing process; one of the key factors that restrict the reliability and yield of integrated circuit chips is overlay error between the layers.

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Cited by 10 publications
(1 citation statement)
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“…From the perspective of overlay correction, the overlay error can be divided into the correctable part and the noncorrectable part. The former part includes inter-field and intra-field overlay, and they can be further corrected by the parameters which describe the geometrical deformation of the wafer and reticle patterns, generally covering the parameters of translation, rotation, magnification, scale and orthogonality, as shown in figure 2 30 . While the latter part cannot be corrected and it is mainly composed of non-systematic overlay and process correction residual 31,32 .…”
Section: Overlay Classificationsmentioning
confidence: 99%
“…From the perspective of overlay correction, the overlay error can be divided into the correctable part and the noncorrectable part. The former part includes inter-field and intra-field overlay, and they can be further corrected by the parameters which describe the geometrical deformation of the wafer and reticle patterns, generally covering the parameters of translation, rotation, magnification, scale and orthogonality, as shown in figure 2 30 . While the latter part cannot be corrected and it is mainly composed of non-systematic overlay and process correction residual 31,32 .…”
Section: Overlay Classificationsmentioning
confidence: 99%