An Empirical Roofline Methodology for Quantitatively Assessing Performance Portability

Yang, Charlene; Gayatri, Rahulkumar; Kurth, Thorsten; Basu, Protonu; Ronaghi, Zahra; Friesen, Brian; Cook, Brandon; Doerfler, Douglas; Oliker, Leonid; Deslippe, Jack; Williams, Samuel

doi:10.1109/p3hpc.2018.00005

Cited by 38 publications

(30 citation statements)

References 9 publications

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“…Here, threads within a warp update access every n th element (threads stride by 32∗ n words instead of the nominal Stride‐32). Unlike our previous work, which focused solely on HBM Rooflines for GPUs, the GPP hierarchical Roofline shows that the L1 and L2 cache behave quite differently from HBM. Whereas HBM intensity decreases linearly with increasing stride up to Stride‐4 (4 double complex words = 64 Bytes), L1 and L2 intensity stops decreasing beyond Stride‐2 (32B).…”

Section: Resultscontrasting

confidence: 65%

“…In this paper, we leverage the proof of concept methodology developed by Yang et al and extend it to support both hierarchical (L1, L2, HBM, System Memory) Roofline analysis as well as FP32 and FP16 precision (including Tensor Core). To that end, we use nvprof to collect a set of metrics for each kernel in an application.…”

Section: Roofline Methodology On Nvidia Gpusmentioning

confidence: 99%

“…In this paper, we extend the nvprof‐based HBM Roofline methodology we developed for NVIDIA GPUs to capture the full NVIDIA GPU memory hierarchy, the effects of FPADD/FPMUL in the instruction mix, the effects of reduced precision FP16 and FP32 Rooflines, and the benefits of using FP16 Tensor Cores (HMMA instructions). To demonstrate the value of this hierarchical GPU Roofline methodology, we used it to analyze three benchmarks: the moderately compute–intensive GPP Material Science proxy application, the cache‐intensive HPGMG AMR‐multigrid proxy application, and the reduced precision and a Tensor Core‐accelerated 2D convolution kernel from TensorFlow.…”

Section: Summary Conclusion and Future Workmentioning

confidence: 99%

“…However, Roofline has yet to be fully developed on NVIDIA GPUs. This paper builds upon the previous work on CPU architectures as well as the HBM‐only Roofline methodology we developed for NVIDIA GPUs and expands the model into a hierarchical Roofline methodology that also captures the performance effects associated with reduced precision and Tensor Cores on NVIDIA's latest V100 GPUs.…”

Section: Introductionmentioning

confidence: 99%

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Hierarchical Roofline analysis for GPUs: Accelerating performance optimization for the NERSC‐9 Perlmutter system

Yang

Kurth

Williams

2019

Concurrency and Computation

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Summary The Roofline performance model provides an intuitive and insightful approach to identifying performance bottlenecks and guiding performance optimization. In preparation for the next‐generation supercomputer Perlmutter at NERSC, this paper presents a methodology to construct a hierarchical Roofline on NVIDIA GPUs and extends it to support reduced precision and Tensor Cores. The hierarchical Roofline incorporates L1, L2, device memory, and system memory bandwidths into one single figure, and it offers more profound insights into performance analysis than the traditional DRAM‐only Roofline. We use our Roofline methodology to analyze three proxy applications: GPP from BerkeleyGW, HPGMG from AMReX, and conv2d from TensorFlow. In doing so, we demonstrate the ability of our methodology to readily understand various aspects of performance and performance bottlenecks on NVIDIA GPUs and motivate code optimizations.

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Section: Resultscontrasting

confidence: 65%

Section: Roofline Methodology On Nvidia Gpusmentioning

confidence: 99%

Section: Summary Conclusion and Future Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Hierarchical Roofline analysis for GPUs: Accelerating performance optimization for the NERSC‐9 Perlmutter system

Yang

Kurth

Williams

2019

Concurrency and Computation

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“…We validated the Roofline model using the Empirical Roofline Tool (ERT) [56]. We re-wrote the micro-kernels in ERT to run them under host and device placement.…”

Section: Roofline Validationmentioning

confidence: 99%

Intelligent Data Placement on Discrete GPU Nodes with Unified Memory

Sultana

Allen

Qasem

2020

Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques

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With increasing heterogeneity, the importance of data organization within a compute node has grown immensely. Recently, industry vendors have introduced technology that can present a unified shared address space for multiple physical pools of memory. In this paper, we leverage unified memory technology and characterize the performance trade-offs of host and device placement across a range of hybrid application design patterns. We perform a Roofline analysis to establish fundamental performance bounds in collaborative applications and then develop an analytical model that makes profitable placement decisions at the individual data structure level. We integrate the placement model into a runtime system and enable transparent data placement in CUDA/C++ applications. Preliminary experiments yield the following results: (i) placement policies have significant performance impact across hybrid application design paradigms (ii) placement decisions are impacted by the sparsity of data access, page re-migration, amount of latency hiding opportunities and design-specific attributes such as the number of pipeline stages, and (iii) intelligent data placement can improve node performance by up to 5× on applications with sparse access patterns. CCS CONCEPTS • General and reference → Performance; • Software and its engineering → Runtime environments.

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FPGA‐based HPC accelerators: An evaluation on performance and energy efficiency

Nguyen

MacLean

Siracusa

et al. 2021

Concurrency and Computation

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Hardware specialization is a promising direction for the future of digital computing. Reconfigurable technologies enable hardware specialization with modest non‐recurring engineering cost, but their performance and energy efficiency compared to state‐of‐the‐art processor architectures remain an open question. In this article, we use FPGAs to evaluate the benefits of building specialized hardware for numerical kernels found in scientific applications. In order to properly evaluate performance, we not only compare Intel Arria 10 and Xilinx U280 performance against Intel Xeon, Intel Xeon Phi, and NVIDIA V100 GPUs, but we also extend the Empirical Roofline Toolkit (ERT) to FPGAs in order to assess our results in terms of the Roofline model. We show design optimization and tuning techniques for peak FPGA performance at reasonable hardware usage and power consumption. As FPGA peak performance is known to be far less than that of a GPU, we also benchmark the energy efficiency of each platform for the scientific kernels comparing against microbenchmark and technological limits. Results show that while FPGAs struggle to compete in absolute terms with GPUs on memory‐ and compute‐intensive kernels, they require far less power and can deliver nearly the same energy efficiency.

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An Empirical Roofline Methodology for Quantitatively Assessing Performance Portability

Cited by 38 publications

References 9 publications

Hierarchical Roofline analysis for GPUs: Accelerating performance optimization for the NERSC‐9 Perlmutter system

Hierarchical Roofline analysis for GPUs: Accelerating performance optimization for the NERSC‐9 Perlmutter system

Intelligent Data Placement on Discrete GPU Nodes with Unified Memory

FPGA‐based HPC accelerators: An evaluation on performance and energy efficiency

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