An Empirical Modeling of Gate Voltage-Dependent Behaviors of Amorphous Oxide Semiconductor Thin-Film Transistors including Consideration of Contact Resistance and Disorder Effects at Room Temperature

Lee, Sungsik

doi:10.3390/membranes11120954

Cited by 3 publications

(3 citation statements)

References 22 publications

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“…Finally, Mo, a widely used electrode material, was deposited and patterned as the gate electrode. 32 A schematic of the fabricated oxide TFT is shown in Figure 1. The fabricated TFTs were annealed at 330 and 350 °C under vacuum conditions.…”

Section: Methodsmentioning

confidence: 99%

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Engineering a Subnanometer Interface Tailoring Layer for Precise Hydrogen Incorporation and Defect Passivation for High-End Oxide Thin-Film Transistors

Ko,

Cho,

Park

2023

ACS Appl. Mater. Interfaces

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Top-gate self-aligned structured oxide thin-film transistors (TFTs) are suitable for the backplanes of high-end displays because of their low parasitic capacitances. The gate insulator (GI) deposition process should be carefully designed to manufacture a highly stable, high-mobility oxide TFT, particularly for a top-gate structure. In this study, a nanometer-thick Al2O3 layer via plasma-enhanced atomic layer deposition (PE-ALD) is deposited on the top-gate bottom-contact structured oxide TFT as the interface tailoring layer, which can also act as the hydrogen barrier to modulate carrier generation from hydrogen incorporation into the active layer of the TFT during the following process such as postannealing. Al-doped InSnZnO (Al/ITZO) with an Al/In/Sn/Zn atomic ratio composition of 1.7:24.3:40:34 was used for high mobility oxide semiconductors, and an Al2O3/Si3N4 bilayer was used for the GI. The degradation issue due to the excellent barrier characteristics of Al2O3 and Si3N4 can be minimized. An oxide TFT fabricated without the interface tailoring layer exhibits conductor-like characteristics owing to the excessive carrier generation by hydrogen incorporation. However, TFTs with additional interface layers exhibit reasonable characteristics and distinct trends in electrical characteristics depending on the thicknesses of the interface layers. The optimized devices exhibit an average turn-on voltage (V on) of −0.31 V with 33.63 cm2/(V s) of high mobility and 0.09 V/dec of subthreshold swing value. The interfaces between the active layer and hydrogen barriers were investigated using a high-resolution transmission electron microscope, contact angle measurement, and secondary ion mass spectroscopy to reveal the origin of the trends in properties between the devices. The top-gate device with a hydrogen barrier using the four-cycle deposition exhibits optimum electrical characteristics of both high mobility and good stability with only a 0.04 V shift of V on under positive-bias temperature stress (PBTS). We realize a high-end, self-aligned TFT with high mobility [34.7 cm2/(V s)] and negligible V on shift of −0.06 V under PBTS by applying a subnanometer hydrogen barrier.

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Section: Methodsmentioning

confidence: 99%

“…Growth per cycle (GPC) was used to calculate the hydrogen barrier thicknesses as 0.25, 0.5, and 1.0 nm, respectively. Finally, Mo, a widely used electrode material, was deposited and patterned as the gate electrode . A schematic of the fabricated oxide TFT is shown in Figure .…”

Section: Methodsmentioning

confidence: 99%

Engineering a Subnanometer Interface Tailoring Layer for Precise Hydrogen Incorporation and Defect Passivation for High-End Oxide Thin-Film Transistors

Ko,

Cho,

Park

2023

ACS Appl. Mater. Interfaces

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“…For this study, we fabricated an array of freestanding graphene variable capacitors on 100 mm silicon wafers. We used standard silicon fabrication processes, along with other well-established techniques developed by the semiconductor industry [ 43 , 44 , 45 , 46 , 47 , 48 , 49 , 50 , 51 ]. However, our graphene-well structure has requirements that make its development unique, and we share the process here.…”

Section: Introductionmentioning

confidence: 99%

Array of Graphene Variable Capacitors on 100 mm Silicon Wafers for Vibration-Based Applications

et al. 2022

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Highly flexible, electrically conductive freestanding graphene membranes hold great promise for vibration-based applications. This study focuses on their integration into mainstream semiconductor manufacturing methods. We designed a two-mask lithography process that creates an array of freestanding graphene-based variable capacitors on 100 mm silicon wafers. The first mask forms long trenches terminated by square wells featuring cone-shaped tips at their centers. The second mask fabricates metal traces from each tip to its contact pad along the trench and a second contact pad opposite the square well. A graphene membrane is then suspended over the square well to form a variable capacitor. The same capacitor structures were also built on 5 mm by 5 mm bare dies containing an integrated circuit underneath. We used atomic force microscopy, optical microscopy, and capacitance measurements in time to characterize the samples.

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Thin-Film Transistors

2022

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An Empirical Modeling of Gate Voltage-Dependent Behaviors of Amorphous Oxide Semiconductor Thin-Film Transistors including Consideration of Contact Resistance and Disorder Effects at Room Temperature

Cited by 3 publications

References 22 publications

Engineering a Subnanometer Interface Tailoring Layer for Precise Hydrogen Incorporation and Defect Passivation for High-End Oxide Thin-Film Transistors

Engineering a Subnanometer Interface Tailoring Layer for Precise Hydrogen Incorporation and Defect Passivation for High-End Oxide Thin-Film Transistors

Array of Graphene Variable Capacitors on 100 mm Silicon Wafers for Vibration-Based Applications

Thin-Film Transistors

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