An Empirical Methodology for Power Analysis of CMOS Integrated Circuits

Abstract

Energy consumption is becoming one of the most significant aspects of CMOS Integrated Circuits (IC), especially for those applied in embedded devices whose autonomy depends upon battery lifespan. Therefore, an empirical methodology for determination of power and energy dissipation may provide valuable information to IC designers, as well as software developers, which could impact design process and lead to more energy-efficient solutions. This paper presents a novel methodology for determination of static and dynamic components of energy dissipation for those CMOS ICs that do not support turning off clock distribution entirely, but provide ability to divide a clock frequency. For that purpose, we used an Eclipse based IDE that provides a user friendly interface for dividing a clock frequency on ultra-low power embedded DSP platform, which was used as a target device. Measurements were performed using a true RMS multimeter. Various experiments were conducted using different scenarios, on single and multi cores, in order to validate the described empirical methodology, and the outcome confirmed what was expected, that the obtained results are stable and accurate.

Power and Energy Consumption Models for Embedded Applications

“…This paper briefly recaps this in Sections IV and V, respectively, since it is important for the overall context. The main contribution of this paper is presented in Section VI, where the models of power and energy estimation are derived using the empirical data and methodologies described by the authors in [2] and [3]. Finally, this research validates not only conclusions and methodologies presented by the authors in [1]- [4], but also derived models in this paper using the classic embedded algorithm such as Finite Impulse Response (FIR) Filter.…”

“…To reach this goal, it was first necessary to identify all key contributors and establish an appropriate methodology to measure energy consumption at the instruction level, the inter-instruction effect, static and dynamic power dissipation [2], [3], as well as the influence of different peripherals and cores on the overall energy balance. Section III provides a brief description of the target hardware platform on which these experiments have been performed.…”