An Embedded Auto-leveling System based on ARM and FPGA

Yang, Hui; Chen, Youping; Chen, Bing

doi:10.11591/telkomnika.v11i12.3741

Cited by 2 publications

(2 citation statements)

References 15 publications

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“…The parameter took around 40.3 seconds for timer, which supplied by 100 MHz clock signal to reach zero. Comparing the approach developed by Yang et.al [12] which combining two separate devices, ARM processor and FPGA, on a PCB, this approach gives less PCB footprint, simplified PCB design and gives better signal integrity.…”

Section: Resultsmentioning

confidence: 99%

Overview of Custom Microcontroller using Xilinx Zynq XC7Z020 FPGA

2015

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This paper presents an overview of customizable microcontroller using a Xilinx Zynq XC7Z020 FPGA as an alternative to increase its performance as user need. This alternative arises due to many of the systems, which developed mostly by using microcontroller are not giving any room for customization to increase its performance or I/O ports. There is any possibility that the system designed to be used by using general processor such as PC to increase its performance but it will give another problem such as interface difficulty for high speed I/O, real time processing, increases complexity, and many more. Customization is introduced by combining hard IP processor and FPGA in one chip instead of practicing two separate devices, processor and FPGA, which is commonly use in high performance embedded design. This approach allows seamless design development and development time reduction for customization.

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Section: Resultsmentioning

confidence: 99%

Overview of Custom Microcontroller using Xilinx Zynq XC7Z020 FPGA

2015

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“…In this paper, we have solved the problem of drawing lengthy straight lines in an extremely short time. Our approach of line segmentation and parallelization in implementing the 3D-Bresenham algorithm on single SoC (System on Chip) [9], [10] is presented. The parallelization approach is to handle several procedures at the same time and execute them independently [11].…”

Section: Introductionmentioning

confidence: 99%

Hardware/software co-design for a parallel three-dimensional bresenham’s algorithm

Ismael¹,

Tareq²,

Qassim³

2019

IJECE

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<p>Line plotting is the one of the basic operations in the scan conversion. Bresenham’s line drawing algorithm is an efficient and high popular algorithm utilized for this purpose. This algorithm starts from one end-point of the line to the other end-point by calculating one point at each step. As a result, the calculation time for all the points depends on the length of the line thereby the number of the total points presented. In this paper, we developed an approach to speed up the Bresenham algorithm by partitioning each line into number of segments, find the points belong to those segments and drawing them simultaneously to formulate the main line. As a result, the higher number of segments generated, the faster the points are calculated. By employing 32 cores in the Field Programmable Gate Array, a line of length 992 points is formulated in 0.31μs only. The complete system is implemented using Zybo board that contains the Xilinx Zynq-7000 chip (Z-7010).<em></em></p>

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An Embedded Auto-leveling System based on ARM and FPGA

Cited by 2 publications

References 15 publications

Overview of Custom Microcontroller using Xilinx Zynq XC7Z020 FPGA

Overview of Custom Microcontroller using Xilinx Zynq XC7Z020 FPGA

Hardware/software co-design for a parallel three-dimensional bresenham’s algorithm

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