An Efficient VLSI Architecture for Discrete Hadamard Transform

Basiri, M. Mohamed Asan; Mahammad, S. K. Noor

doi:10.1109/vlsid.2016.63

Cited by 5 publications

(1 citation statement)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Digital signal processing (DSP) operations such as convolution, correlation, filtering [1], and transformations [2][3][4] are in the form of multiplication and repeated addition. Therefore, multiply accumulate circuit (MAC) [5] is the basic element of any digital signal processor.…”

Section: Introductionmentioning

confidence: 99%

Quadruple throughput fixed point quarter precision multiply accumulate circuit design

Basiri

Mohammad

2017

IET Computers & Digital Techniques

View full text Add to dashboard Cite

This study proposes an efficient very large scale integration (VLSI) architecture for quadruple throughput fixed point multiply accumulate circuit (MAC). The proposed n × n bits MAC is used to perform one n × n bits or two n × (n/2) bits or four (n/2) × (n/2) bits MAC operations in parallel. The objective of the proposed MAC is to improve throughput of the existing MAC designs. The proposed and existing designs are implemented by 45 nm CMOS TSMC library and the results show that the proposed architecture achieves better improvement in throughput than existing designs. For example, the proposed 32 × 32 bits MAC architecture achieves 60.4% of improvement in throughput over existing array multiplier-based double throughput MAC.

show abstract

Section: Introductionmentioning

confidence: 99%