An efficient VLSI architecture for discrete wavelet transform

Hsia, Chih-Hsien; Yang, Jia-Hao

doi:10.1109/apsipa.2015.7415359

Cited by 3 publications

(1 citation statement)

References 13 publications

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“…Even though it reduced the power the architecture is more complex with larger area occupation on FPGA. An interlacing coding is suggested for the image interfacing in SVC is outlined in [2]. A brief outline to image coding using SVC and AVC interlacing is suggested.…”

Section: Related Workmentioning

confidence: 99%

Implementation of a Novel Adaptive Coding using VLSI Architecture for Data Compression in Image Processing

2023

Preprint

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: Image Compression is one of the emerging techniques of a Digital System for storing and retrieving of digital information. The main challenge in implementing Image Compression is to maintain the accuracy of the retrieved data. As the encoding techniques used for data compression are computationally intensive, new hardware architectures are required so that the processing of image consumes less space with increase in computation speed, reduction in area and power consumption. In this paper we address this problem and developed an Adaptive coding technique and implemented using VLSI architecture. An adaptive compression model using dynamic code allocation based on probability of occurrence is proposed. Here the Entropy code has a maximum search overhead of 6 match per 4-bit pattern. Wherein a maximum of 5-bit search is observed in proposed approach. This reduces a search overhead of (N⨉m)-1 iterations. Here N is the number of unique patterns and m is the block size. The proposed architecture is developed using VHDL language and implemented using Xilinx Aldec’s FPGA. The adaptive coding approach attains a compression of 35% more as compared to the entropy coding. The implementation on to targeted Xilinx FPGA results in power minimization and area coverage reduction. The speed of operation is observed to be improved by 135MHz. The validation of proposed approaches is made on image data to observe the coding accuracy. The mean square error of the output image is reduced by 35% with an increase in the signal to noise ratio of the output image.

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Section: Related Workmentioning

confidence: 99%

Implementation of a Novel Adaptive Coding using VLSI Architecture for Data Compression in Image Processing

2023

Preprint

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Implementation of a novel adaptive coding using VLSI architecture for data compression in image processing

Kiranmaye,

Sridhar

2024

Multimed Tools Appl

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Multiplier Free Implementation of 8-Tap Daubechies Wavelet Filters for Biomedical Applications

Coskun¹,

Kale²,

Eminaga³

2017

2017 New Generation of CAS (NGCAS)

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obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The WestminsterResearch online digital archive at the University of Westminster aims to make the research output of the University available to a wider audience. Copyright and Moral Rights remain with the authors and/or copyright owners.Whilst further distribution of specific materials from within this archive is forbidden, you may freely distribute the URL of WestminsterResearch: ((http://westminsterresearch.wmin.ac.uk/). Abstract-Due to an increasing demand for on-sensor biosignal processing in wireless ambulatory applications, it is crucial to reduce the power consumption and hardware cost of the signal processing units. Discrete Wavelet Transform (DWT) is very popular tool in artifact removal, detection and compression for time-frequency analysis of biosignals and can be implemented as two-branch filter bank. This work proposes a new, completely multiplier free filter architecture for implementing Daubechies wavelets which targets Field-Programmable-Gate-Array (FPGA) technologies by replacing multipliers with Reconfigurable Multiplier Blocks (ReMBs). The results have shown that the proposed technique reduces the hardware complexity by 40% in terms of Look-Up Table (LUT) count and can be used in low-cost embedded platforms for ambulatory physiological signal monitoring and analysis.

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An efficient VLSI architecture for discrete wavelet transform

Cited by 3 publications

References 13 publications

Implementation of a Novel Adaptive Coding using VLSI Architecture for Data Compression in Image Processing

Implementation of a Novel Adaptive Coding using VLSI Architecture for Data Compression in Image Processing

Implementation of a novel adaptive coding using VLSI architecture for data compression in image processing

Multiplier Free Implementation of 8-Tap Daubechies Wavelet Filters for Biomedical Applications

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