An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform

Wang, Chao; Wu, Zhilin; Cao, Peng; Li, Jie

doi:10.1109/icme.2007.4284965

Cited by 5 publications

(5 citation statements)

References 6 publications

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“…By substituting formula (3) into formula (4), the first lifting step can be a new expression as shown in formula (9). In the same way, the second lifting step can be a new expression as shown in formula (10). First Lifting Step:…”

Section: Proposed Hardware Architecutementioning

confidence: 98%

“…Column filter module can be regarded as a 1-D DWT processor on the column wise, and is composed of two column lifting elements. Data flow of a column lifting element for (9,7) wavelet filter can be obtained from formula (9) as shown in Fig.3, and in the same way data flow of another lifting element can be obtained from formula (10). We can know from the Fig.3, one input sample is read and multiplied by a constant coefficient in each cycle.…”

Section: Column Filter Modulementioning

confidence: 98%

“…That requirement is met by using intermediate transposing memory in references [7], [9] and [10], but using intermediate transposing memory occupies quite large internal memory space. We adopt 2×2 transposing module which only uses 2 registers instead of 1.5M size intermediate transposing memory space.…”

Section: ×2 Transposing Modulementioning

confidence: 99%

“…Scaling module, shown in Fig.6, is applied in reference [10] for completing 2-D DWT. The scaling arithmetic needs 2 multipliers.…”

Section: Scaling Modulementioning

confidence: 99%

“…The pipelined technique can reduce the critical path and increase the working frequency of the system, but it also increases the hardware overhead [5]- [7]. Flipping structure, which is more beneficial to hardware implementation, skillfully flips and combines the coefficients of the lifting structure, reduces the multiplication and addition computation times, but uses more internal registers, internal memories and hardware multiplexer resources [8]- [10]. On the basis of flipping structure, we propose a high performance hardware implementation architecture.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

High Performance Hardware Implementation Architecture for DWT of Lifting Scheme

Hao¹,

Liu²,

Wang³

2008

2008 International Conference on Intelligent Information Hiding and Multimedia Signal Processing

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On the problem that the hardware overhead of hardware implementation architecture for discrete wavelet transform wastes a lot, on the basis of flipping structure, we propose a high performance hardware implementation architecture. The architecture merges the lifting step and adopts the pipelined design to adjust the primitive data path. The proposed 2-D DWT architecture consists of four parts: column filter module, 2×2 transposing module, row filter module and scaling module. The column filter and row filter process simultaneously. The 2×2 transposing module makes it true that several registers substitute a lot of intermediate transposing memory. The architecture introduces 4 to 1 multiplexer into scaling module. Experimental results show that the proposed architecture, under the tight critical path, can efficiently reduce the hardware overhead and save the hardware power.

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Section: Proposed Hardware Architecutementioning

confidence: 98%

Section: Column Filter Modulementioning

confidence: 98%