An efficient timing model for hardware implementation of multirate dataflow graphs

Abstract

We consider the problem of representing timing information associated with functions in a dataflow graph used to represent a signal processing system in the context of high-level hardware (architectural) synthesis. This information is used for synthesis of appropriate architectures for implementing the graph. Conventional models for timing suffer from shortcomings that make it difficult to represent timing information in a hierarchical manner, especially for multirate signal processing systems.We identify some of these shortcomings, and provide an alternate model that does not have these problems. We show that with some reasonable assumptions on the way hardware implementations of multirate systems operate, we can derive general hierarchical descriptions.of multirate systems similarly to single rate systems. Several analytical results such as the computation of the iteration period bound, that previously applied only to single rate systems can also easily be extended to multirate systems under the n e w assumptions.We have applied our model to several multirate signal processing applications, and obtained favorable results. We present results of the timing information computed for several multirate DSP applications that show how the new treatment can streamline the problem of performance analysis and synthesis of such systems.

An empirical characterization of stream programs and its implications for language and compiler design

“…For example, MP3 reorders and adds data across large (>1000 item) sliding windows; 802.11 and Trellis do short (3-7 item) bit-wise operations as part of an error-correcting code; Vocoder and Audiobeam use peeking to skip N items (by default [1][2][3][4][5][6][7][8][9][10][11][12][13][14], analogous to an inverse delay; ChannelVocoder performs a sliding autocorrelation and threshold across N items (by default 100).…”

“…For example, the CD-DAT benchmark (shown in Figure 5) is used in many studies [3,4,10,31,39,40,50]; it converts compact disk auto (sampled at 44.1 khz) to digital audio tape (sampled at 48 khz). Performing this conversion in stages improves efficiency [39].…”

Hierarchical Pipelining of Nested Loops in High-Level Synthesis

“…In order to form an acyclic graph, the operations inside each cycle 4 has to be substituted by a single operation first. Let L(G) the latency of graph G (as an MR-HSDFG) as the sum of the duration times of the longest path in G. The calculation of the minimal restart time is shown for the three cases as follow:…”

“…It is beneficial to perform the pipeline scheduling method on a dataflow representation, because these are formal and abstract models of a system. The operations inside a loop body are executed more times than the program itself, therefore a so-called multi-rate dataflow model [14,10,4] can be applied to represent nested loops. The well known multi-rate dataflow graphs (e.g.…”

Consistency Analysis of Reconfigurable Dataflow Specifications

“…The VSDF [13] and multirate hierarchical timing pair (MHTP) [7] models are dataflow modeling techniques that are geared towards efficient hardware implementation.…”