An efficient STT-RAM last level cache architecture for GPUs

Samavatian, Mohammad Hossein; Abbasitabar, Hamed; Arjomand, Mohammad; Sarbazi-Azad, Hamid

doi:10.1109/dac.2014.6881524

Cited by 13 publications

(10 citation statements)

References 11 publications

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“…STT-MRAM has been widely studied as an on-chip cache [17][18][19][20], and few studies have used it as a main memory. Meza et al [21] showed that reducing the size of the row buffer can greatly reduce the dynamic energy of the NVM main memory.…”

Section: Related Workmentioning

confidence: 99%

Optimized fast data migration for hybrid DRAM/STT-MRAM main memory

Liu

Chen

Hao

et al. 2022

IEICE Electron. Express

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In order to reduce the main memory energy of the IoT terminal, STT-MRAM is used to replace DRAM to save refresh energy. However, the write performance of STT-MRAM cells is worse than that of DRAM. Our previous work proposed a hybrid DRAM/STT-MRAM main memory and fast data migration to reduce the adverse effects of poor write performance of STT-MRAM cells with negligible performance overhead. This article optimizes the migration algorithm and experiment scheme: 1. Reduce the storage overhead of the algorithm. 2. Realize the continuous work of the algorithm. 3. Consider the impact of system standby time on main memory energy. The results show that compared with our previous work, the storage overhead of the algorithm is reduced 99.8%. When the system standby time is zero, the energy of the hybrid main memory (including the energy of the algorithm) is reduced by 4% on average compared to DRAM. The longer the system standby time, the more energy saving.

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Section: Related Workmentioning

confidence: 99%

Optimized fast data migration for hybrid DRAM/STT-MRAM main memory

Liu

Chen

Hao

et al. 2022

IEICE Electron. Express

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“…There also exist prior efforts that try to incorporate NVM in a GPU memory hierarchy. Samavatian et al [57] presents a new L2 cache that integrates low-retention STT-MRAM and long-retention STT-MRAM arrays. To reduce the write penalty of STT-MRAM, [57] proposes to store write-intensive data in lowretention STT-MRAM and store read-only data in highretention STT-MRAM.…”

Section: Related Workmentioning

confidence: 99%

FUSE: Fusing STT-MRAM into GPUs to Alleviate Off-Chip Memory Access Overheads

Zhang

Kandemir

2019

2019 IEEE International Symposium on High Performance Computer Architecture (HPCA)

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In this work, we propose FUSE, a novel GPU cache system that integrates spin-transfer torque magnetic random-access memory (STT-MRAM) into the on-chip L1D cache. FUSE can minimize the number of outgoing memory accesses over the interconnection network of GPU's multiprocessors, which in turn can considerably improve the level of massive computing parallelism in GPUs. Specifically, FUSE predicts a read-level of GPU memory accesses by extracting GPU runtime information and places write-once-read-multiple (WORM) data blocks into the STT-MRAM, while accommodating write-multiple data blocks over a small portion of SRAM in the L1D cache. To further reduce the off-chip memory accesses, FUSE also allows WORM data blocks to be allocated anywhere in the STT-MRAM by approximating the associativity with the limited number of tag comparators and I/O peripherals. Our evaluation results show that, in comparison to a traditional GPU cache, our proposed heterogeneous cache reduces the number of outgoing memory references by 32% across the interconnection network, thereby improving the overall performance by 217% and reducing energy cost by 53%.

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“…For NVIDIA Pascal [57], more than 60% of the on-chip storage area, amounting to 14.3 MB is dedicated to the register file. GPU register files face the difficult challenge of optimizing latency, bandwidth, and power consumption, while having maximal capacity [2,19,20,23,25,27,28,39,43,45,46,48,65,66,78,79,80]. Larger register files are slower, take up more silicon area and consume more power.…”

Section: Register File Scalabilitymentioning

confidence: 99%

LTRF

Sadrosadati

Mirhosseini

Ehsani

et al. 2018

Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Syste

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Graphics Processing Units (GPUs) employ large register files to accommodate all active threads and accelerate context switching. Unfortunately, register files are a scalability bottleneck for future GPUs due to long access latency, high power consumption, and large silicon area provisioning. Prior work proposes hierarchical register file, to reduce the register file power consumption by caching registers in a smaller register file cache. Unfortunately, this approach does not improve register access latency due to the low hit rate in the register file cache. In this paper, we propose the Latency-Tolerant Register File (LTRF) architecture to achieve low latency in a two-level hierarchical structure while keeping power consumption low. We observe that compile-time interval analysis enables us to divide GPU program execution into intervals with an accurate estimate of a warp's aggregate register working-set within each interval. The key idea of LTRF is to prefetch the estimated register working-set from the main register file to the register file cache under software control, at the beginning of each interval, and overlap the prefetch latency with the execution of other warps. Our experimental results show that LTRF enables high-capacity yet long-latency main GPU register files, paving the way for various optimizations. As an example optimization, we implement the main register file with emerging high-density high-latency memory technologies, enabling 8× larger capacity and improving overall GPU performance by 31% while reducing register file power consumption by 46%.

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An efficient STT-RAM last level cache architecture for GPUs

Cited by 13 publications

References 11 publications

Optimized fast data migration for hybrid DRAM/STT-MRAM main memory

Optimized fast data migration for hybrid DRAM/STT-MRAM main memory

FUSE: Fusing STT-MRAM into GPUs to Alleviate Off-Chip Memory Access Overheads

LTRF

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