An Efficient SRAM yield Analysis Using Scaled-Sigma Adaptive Importance Sampling

Pang, Liang; Yao, Mengyun; Chai, Yifan

doi:10.23919/date48585.2020.9116233

Cited by 4 publications

(3 citation statements)

References 16 publications

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“…The parasitic parameters are directly extracted from post-layout circuits. Besides, we also implement OMP [7], LRTA [8] for model comparison and SSAIS [2], HDIS [3] for yield estimation comparison. All experiments are performed with MATLAB and HSPICE with 28nm TSMC model on the Server with Intel Xeon Gold 5118 CPU @ 2.30 GHz.…”

Section: Experiments Resultsmentioning

confidence: 99%

A High Dimensional and High Sigma Statistical Model for SRAM Read Access Yield Estimation

Zhang,

Li,

Yan

2024

Preprint

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High dimensional statistical analysis for the yield of large-scale circuits is quite difficult due to expensive simulations, especially for the memory circuits with high sigma requirement (e.g., SRAM). In this paper, we developed an efficient sparse additive model to substitute simulations. To fit high sigma region accurately, the modeling center is moved to near failure boundary searched by scaling the shape of sampling function. To solve the model efficiently, the process variables are grouped by standard cells so that the model can be solved by our developed blockwise greedy algorithm. The experiments on the 28nm memory circuits validate that our method achieves high accuracy and efficiency compared with other state-of-art works.

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Section: Experiments Resultsmentioning

confidence: 99%

A High Dimensional and High Sigma Statistical Model for SRAM Read Access Yield Estimation

Zhang,

Li,

Yan

2024

Preprint

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“…From the previous subsections, fVOS(v), FVBL(vbl|TWL2SAE = t), and fTWL2SAE(t) can be obtained, that is, all the forms required to derive Pfail,bitcell (and therefore YR) in (6) are available. The double integration in (6) for Pfail,bitcell derivation can be interpreted as the two following steps; 1) the CDF of VBL at TWL2SAE, FVBL(v), is derived first as (26), and 2) subsequently, the probability that the measured VBL is smaller than VOS is derived. This article has been accepted for publication in a future issue of this journal, but has not been fully edited.…”

Section: Derivation Of Bitcell Failure Ratementioning

confidence: 99%

“…There are two remarkable points in (5) and (6). First, if the target YR is sufficiently high, requiring an extremely low individual bitcell failure rate (e.g., 6 sigma yield) that is the typical case, only NBIT is significant when YR is to be determined, while the individual values of NSA, NROW, and NCOL are unimportant.…”

Section: Introductionmentioning

confidence: 99%

High-Density SRAM Read Access Yield Estimation Methodology

Baek

Jeong

2021

IEEE Access

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As high-density SRAMs must be designed to ensure a substantially small failure rate, the accurate yield estimation with practically acceptable runtime of circuit simulations is highly challenging. Here, a read access yield estimation method for high-density static random access memory (SRAM) is proposed. Instead of performing SPICE runs for the entire SRAM circuit, the proposed method partitions the SRAM into three parts-the control signal generation circuit, bitcell array, and sense amplifier (SA)that determine three key parameters: word-line to SA enable delay, bit-line voltage difference, and SA offset voltage. Subsequently, the proposed method derives the probability density of these key parameters from each of the three partitioned circuits. Here, different methods are applied to derive the probability of the key parameters, considering the respective characteristics of each circuit part and parameter. According to our experimental results, the proposed method can accelerate the yield estimation by 500-3000×, compared with the brute-force Monte Carlo simulation method, and 10-100× compared with the other state-of-art methods. In addition, the proposed method can accelerate the circuit optimization procedure accompanied by multiple circuit revisions, that is, the circuit revisions can be reflected with SPICE runs only for the revised circuit part, unlike the previous methods that require SPICE runs for the entire SRAM.INDEX TERMS Process variation, read access yield, sensing yield, static random access memory (SRAM), yield estimation.

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A Spline-High Dimensional Model Representation for SRAM Yield Estimation in High Sigma and High Dimensional Scenarios

2021

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Traditional Static Random-Access Memory (SRAM) yield estimation through Monte Carlo analysis is an extremely time-consuming process since it runs millions of expensive transistor-level simulations to get the yield results with the specified precision, especially for the large-scale circuits. In this paper, we develop an efficient yield analysis framework by integrating our novel performance metamodel into a state-of-art importance sampling method. The performance meta-model, named Spline-High Dimensional Model Representation (SP-HDMR), is used to substitute the expensive transistor-level simulations in yield estimation. The proposed SP-HDMR model provides a high computationally efficient formula expansion. It uses spline functions as the kernels to describe the various relations between the process parameters and SRAM read access delay. And an adaptive sampling method with sparsity analysis is developed to support SP-HDMR modeling. The experiments on the 40nm SRAM circuits validate the accuracy and the efficiency of the proposed yield analysis framework based on our SP-HDMR model with 1.3X~5X speedup over the other state-of-art methods within 9% relative error.

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An Efficient SRAM yield Analysis Using Scaled-Sigma Adaptive Importance Sampling

Cited by 4 publications

References 16 publications

A High Dimensional and High Sigma Statistical Model for SRAM Read Access Yield Estimation

A High Dimensional and High Sigma Statistical Model for SRAM Read Access Yield Estimation

High-Density SRAM Read Access Yield Estimation Methodology

A Spline-High Dimensional Model Representation for SRAM Yield Estimation in High Sigma and High Dimensional Scenarios

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