An efficient post-processing method for pipelined pseudo-random number generator in SoC-FPGA

Abstract

Pseudo-random number generators (PRNGs) are one of the common parts of digital systems used in cryptography, diagnostics, simulation and in many other areas of modern science and technology. Here we present a novel architecture of the PRNG based on the chaotic nonlinear model and pipelined data processing. A significant enhancement in terms of output throughput has been achieved by combining the advantages of pipelining with post-processing based on fast logical operations like bit shifting and XOR. The proposed method has been implemented using programmable SoC Zynq device from Xilinx and verified by standard statistical tests NIST SP800-22. For PRNGs based on the logistic chaotic map and frequency dependent negative resistance (FDNR) we obtained speed-up factors equal to 33% and 14%, respectively. We also present detailed comparison of the proposed post-processing method with the methods reported previously by the other authors. In particular, we compared the maximum output throughput and amount of total logical resources required by PRNG implementation in the programmable SoC device. The maximum output throughput of the proposed PRNG is equal to 38.44 Gbps and is significantly greater comparing to the chaotic PRNGs described so far.

Chaotic Encryption Applied to Optical Ethernet in Industrial Control Systems

“…In Table IV, a comparison in terms of hardware resources is made with other chaotic implementations. Particularly, solutions implementing the logistic map [39], modified logistic map [28], Bernoulli [30], and Hennon [29] maps are shown. While in Tables II and III, the overall hardware resources of this solution are shown, and in Table IV, only the hardware relative to the STM cell is taken into account.…”

“…On the other hand, a second approach is the discrete chaosbased cryptosystems, where one or more chaotic maps are implemented using finite precision and they do not depend on chaos synchronization at all. Many hardware implementations have been proposed for a wide variety of chaotic maps such as in [28], [29], or [30] where the well-known modified logistic map, Hennon map, and Bernoulli map, respectively, were built. Although there are analog solutions that have been digitized, as in [20], the discrete chaos-based approach is more suitable for digital hardware platforms as FPGAs.…”

8-Bit Quantizer for Chaotic Generator With Reduced Hardware Complexity

“…Its mathematical description originally was delimitedfrom'0'to'1'.Thepseudorandomnumbersareusedfordifferentprocess.Cryptography strengthreliesonnumberrandomness (Hohenbergeretal.,2015).Manyotherprocessesarethere whererandomnessishighlydesired,testingandgeneticalgorithmaregoodexample (Dutta,etal. 2014),andanyprocesswheredatamustbeuniformeither.Fromtherigorousliteraturereviewof publishedandexistingwork,itisobservedthatnumerousresearchershaveimplementedrandom numbergeneratorbyusingdifferenttechniques.Differentsystems,processesandphenomenaare takenbytheresearchersfortheanalysisanddesignRNGcontentandattemptedtofindtheunknown parameters.Analgorithmusedtogeneratethesequenceofnumbersthatpossessesthepropertiesof randomnumberarepseudo-randomnumbergenerator,andthesenumberarenottrulyrandom,but thesesequenceareclosertorandomifthesesequencesaregeneratedusinghardwarerandomnumber generators.Inthefieldofcryptographyandsimulations(e.g.,ofphysicalsystemswiththeMonte Carlomethod),pseudorandomnumberplayanimportantrole.However,moderncommunication systems(includingmobilesystems)requiretheuseofadvancedmethodsofinformationprotection against unauthorized access (Dabal & Pelka, 2012). Therefore, one of the essential problems of moderncryptographyisthegenerationofkeyshavingrelevantstatisticalproperties.Inrecentyears, attentiontowardsthedigitalsystemwhicharebasedonthechaostheoryincreasesbycryptanalysts.…”

FPGA-based Chaotic Cryptosystem by Using Voice Recognition as Access Key

“…Other FPGA implementations of chaotic systems and maps have been applied to image encryption [29]. In the same way, the authors in [30] implemented a Chaotic Pseudo-Random Number Generator (CPRNG) in an FPGA using the System Generator tool (SysGen) developed by Xilinx. With respect to patterns recognition for biometric and medical applications, several works have been reported in the literature, see for example [31][32][33][34][35].…”