An Efficient Performance-Driven Approach for HW/SW Co-Design

Proceedings of the 10th and 8th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures

Fiorilli

Mascio

2019

Self Cite

Heterogeneous multi-processor platforms are becoming widely diffused in the embedded system domain, mainly because of the opportunity to improve timing performance and, at the same time, to minimize energy/power consumption and costs. In using such kind of platforms, to be able to consider the trade-offs among different goals, a Design Space Exploration (DSE) is generally adopted. For this, existing DSE approaches typically rely on evolutionary algorithms to solve Multi-Objective Optimization Problems (MOOP) by minimizing a linear combination of weighted objective functions (i.e., Weighted Sum Method, WSM). The problem is then shifted towards the identification of weights able to represent desired tradeoffs. In such a context, this paper focuses on DSE for heterogeneous multi-processor embedded systems and introduces an approach that, while still driven by a "decision maker", is able to self-tune weights to equalize objective functions contribution. In particular, this work presents a self-equalized WSM integrated into a genetic algorithm used to identify sub-optimal implementation alternatives in the context of an Electronic System Level HW/SW Co-Design flow. CCS CONCEPTS • Computer systems organization → Embedded systems; Embedded hardware.

Section: Reference Design Space Exploration Approachmentioning

confidence: 99%

Section: Reference Design Space Exploration Approachmentioning

confidence: 99%

Tuning DSE for Heterogeneous Multi-Processor Embedded Systems by means of a Self-Equalized Weighted Sum Method

Proceedings of the 10th and 8th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures

Fiorilli

Mascio

2019

Self Cite

“…The System Description step defines three reference models: the Application, Architecture and Communication Model. The first model exploits a behavioral modeling language, named HML (HEPSY Modeling Language) [8], based on the CSP MoC [9]. The second model defines the basic HW components available to build the final HW architecture.…”

Section: Hw/sw Co-design Flow With MC Constraintsmentioning

confidence: 99%

Criticality-aware Design Space Exploration for Mixed-Criticality Embedded Systems

Companion of the 2018 ACM/SPEC International Conference on Performance Engineering

Valente

Pomante

2018

Self Cite

“…In the second case, CC4CS is useful since several ESL HW/SW timing co-simulations approaches (e.g. [10] [12]) rely on the availability of an estimated execution time for each statement composing the ESL specification.…”

Section: Exploitation Of Cc4cs In Hw/sw Domainmentioning

confidence: 99%

Cc4cs

Companion of the 2018 ACM/SPEC International Conference on Performance Engineering

Valente

Pomante

et al. 2018

Self Cite

Outlining the general characteristics of embedded systems is an arduous task. In fact, the design of such kind of systems is heavily influenced by functional and non-functional requirements, and it is based on quite complex design flows. So, there is often the need to adopt a HW/SW co-design methodology able to support the designers during high-level phases so that they can perform early analysis before dealing with low-level ones. Such a methodology, to be effective, should consider also performance estimation and ESL HW/SW timing co-simulation. The goal of this paper is to introduce a novel and fast performance metric able to speed-up the early analysis and design space exploration to identify the more promising architectures for different application domains. In particular, the paper presents a framework to evaluate such a metric and to perform some preliminary analysis to evaluate its meaningfulness when exploited in the HW/SW domain.