An efficient numerical-based crosstalk avoidance codec design for NoCs

Shirmohammadi, Zahra; Mozafari, Fereshte; Miremadi, Seyed Ghassem

doi:10.1016/j.micpro.2017.01.003

Cited by 15 publications

(8 citation statements)

References 11 publications

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“…The obtained results of 28nm technology bus encoding method have been compared with different techniques used for minimizing crosstalk. [16][17][18][19]. Existing-I [16] 43375.53 Existing-II [17] 40214.31 LUT-BED [18] 706397 LUT-BED-CLA- [19] 26821 28nm…”

Section: Resultsmentioning

confidence: 99%

The reduction of Crosstalk in VLSI due to parallel bus structure using Data Compression Bus Encoding technique implemented on Artix 7 FPGA Architecture

Yarlagadda¹

2021

ITII

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In this work, a bus encoding method is proposed that reduces the effect of crosstalk. The crosstalk usually occurs when the data is in parallel communicated. In planar structures, the crosstalk effect is large due to the usage of parallel communication and wide data patterns. In bus technique, the huge amount of wires is laid in equal over a significant time. One way to reduce crosstalk without changing the parallel communicating data lines is to reduce the wideband data patterns so as to reduce the power utilization. The proposed encoding method can minimize the crosstalk by reducing wide data patterns without degrading the performance. The architecture is implemented on Artix 7 FPGA at a 28nm technology node. The simulation is done using the HDL tool and the results are compared with the existing FPGA architecture. With the proposed method, the wire density and the power consumption are reduced by 57.4% and 50% respectively as compared with existing 45 nm technologies.

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Section: Resultsmentioning

confidence: 99%

The reduction of Crosstalk in VLSI due to parallel bus structure using Data Compression Bus Encoding technique implemented on Artix 7 FPGA Architecture

Yarlagadda¹

2021

ITII

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“…So, not possible to get a proper crosstalk rectifying signal in the output. Z. Shirmohammadi, F. Mozafari, and S.G. Miremadi [20] has proposed an overhead-efficient coding mechanism called Penultimate-Subtracted Fibonacci (PS-Fibo) to alleviate crosstalk faults in NoC wires. PS-Fibo coding mechanism benefits the novel numerical system that not only completely removes TODs but also, is applicable to a wide range of NoC channel widths.…”

Section: Related Workmentioning

confidence: 99%

“…The comparison of area, power, delay, APP, and ADP for different technologies such as 180nm and 45nm is given in Table 1. In this table, five methods have been compared such as Existing-I [14], Existing-II [20], 18T-FA-BEM, LUT-BED, and LUT-BED-CLA for both 180nm and 45nm. These five method are implemented by Verilog and the outputs are tabulated.…”

Section: Delaymentioning

confidence: 99%

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ASIC Implementation of Low Power Efficient Crosstalk Analytical by LUT-BED-CLA

Obulesu¹,

Rao²

2018

IJIES

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Nowadays, crosstalk noise is one of the major problems in VLSI design circuits. While transmitting the input information, the noise occurs in the channel. After receiving the information, the input data affect by the crosstalk. In this paper, Look Up table with Bus Encoding Decoding Carry Look Ahead adder (LUT-BED-CLA) is introduced to eliminate the crosstalk noise in the receiver side. Encoder block consists of transition detector, Type-A detector, Type-B detector, XOR stack, and Latch. Encoder output is given to the crosstalk model circuit, which is implemented in Cadence virtuoso. This crosstalk model output connects to decoder input. Decoder block contains an XOR circuit to retrieve the original data, which is given to the input of the encoder. From the encoder and decoder, the area, power, and delay was evaluated. Instead of using normal adder, CLA adder was used in counter which gave better performance. Form the crosstalk analysis, cross talk output was given to the decoder input. Even though, decoder output gave same output which was given to the encoder input. This entire work implemented in Verilog to evaluate ASIC performance for 180nm and 45nm technology. In ASIC 180nm technology, 26.3% of area, 39.67% of power, 55.53% of APP, and 26.3% of ADP is minimized in LUT-BED-CLA as well as 45nm technology, 34.4% of area, 24.1% of power, 38.62% of delay, 50.11% of APP, and 59.6% of ADP reduced in LUT-BED-CLA method compared to existing method.

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“…A high-performance coding mechanism called Penultimate-Subtracted Fibonacci is proposed to alleviate crosstalk faults in NoC links (Shirmohammadi et al, 2017). This mechanism benefits the advantages of a new numerical system that does not only completely eliminate triplet opposite direction but also is applicable in a wide range of NoC channel widths.…”

Section: Introductionmentioning

confidence: 99%

Reducing the number of passing links in the 2D-NoC for performance and reliability improvement

Chabok

Alavi

2020

WJE

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Purpose The routing algorithm is one of the most important components in designing a network-on-chip (NoC). An effective routing algorithm can cause better performance and throughput, and thus, have less latency, lower power consumption and high reliability. Considering the high scalability in networks and fault occurrence on links, the more the packet reaches the destination (i.e. to cross the number of fewer links), the less the loss of packets and information would be. Accordingly, the proposed algorithm is based on reducing the number of passed links to reach the destination. Design/methodology/approach This paper presents a high-performance NoC that increases telecommunication network reliability by passing fewer links to destination. A large NoC is divided into small districts with central routers. In such a system, routing in large routes is performed through these central routers district by district. Findings By reducing the number of links, the number of routers also decreases. As a result, the power consumption is reduced, the performance of the NoC is improved, and the probability of collision with a faulty link and network latency is decreased. Originality/value The simulation is performed using the Noxim simulator because of its ability to manage and inject faults. The proposed algorithm, XY routing, as a conventional algorithm for the NoC, was simulated in a 14 × 14 network size, as the typical network size in the recent works.

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An efficient numerical-based crosstalk avoidance codec design for NoCs

Cited by 15 publications

References 11 publications

The reduction of Crosstalk in VLSI due to parallel bus structure using Data Compression Bus Encoding technique implemented on Artix 7 FPGA Architecture

The reduction of Crosstalk in VLSI due to parallel bus structure using Data Compression Bus Encoding technique implemented on Artix 7 FPGA Architecture

ASIC Implementation of Low Power Efficient Crosstalk Analytical by LUT-BED-CLA

Reducing the number of passing links in the 2D-NoC for performance and reliability improvement

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