An efficient multiplier by pass transistor logic partial product and a modified hybrid full adder for image processing applications

Rafiee, Mahmood; Pesaran, Farshad; Sadeghi, Ayoub; Shiri, Nabiollah

doi:10.1016/j.mejo.2021.105287

Cited by 15 publications

(6 citation statements)

References 29 publications

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“…Using approximations in the voltage references employed in the circuit is a third strategy. The reference circuit's complexity can be decreased by approximations, leading to a simpler, more effective circuit [11]. This is one of the approximation methods discussed in the study.…”

Section: Approximation Techniques Strategymentioning

confidence: 99%

“…With the transistor scaling approach, the transistor size is decreased while the circuit's performance is maintained. This is so that smaller transistors can flip more quickly and with less energy needed since they have reduced gate capacitance [11].…”

Section: Transistor Scalingmentioning

confidence: 99%

“…However, this may result in a slight loss of precision in the output of an approximate adder. Another method for streamlining the circuit design is to approximate the voltage references used in the circuit [11]. Approximations can decrease the complexity of the reference circuit, resulting in a more efficient and straightforward circuit.…”

Section: Approximate Addersmentioning

confidence: 99%

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Design of 4-bit absolute value detector with low energy

Zhang

2023

J. Phys.: Conf. Ser.

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The article highlights the latest developments in the design of low-power 4-bit Absolute Value Detector (AVD) circuits that are utilized in digital signal processing (DSP) applications. DSP applications like audio and video processing, biological signal processing, and digital communication systems rely heavily on the AVD circuit, which determines the absolute value of an input signal. The article introduces a low-energy 4-bit AVD circuit based on pass transistors that incorporates advanced optimization techniques like adiabatic logic, approximation techniques, and layout optimization. This optimized AVD circuit achieves remarkable results in terms of power consumption and energy efficiency. With a power consumption of just 0.6 nW and an energy efficiency of 0.6 pJ per cycle, the circuit maintains precision and rapid response time. These advancements in AVD circuit design can be highly beneficial for portable and battery-powered devices such as earplugs, implants, and cell phones, as well as electronic components like Static Random Access Memory (SRAM) and motherboards. Overall, the proposed low-energy 4-bit AVD circuit is a significant development in the DSP field, enabling more efficient and effective processing of digital signals.

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Section: Approximation Techniques Strategymentioning

confidence: 99%

Section: Transistor Scalingmentioning

confidence: 99%

Section: Approximate Addersmentioning

confidence: 99%

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Design of 4-bit absolute value detector with low energy

Zhang

2023

J. Phys.: Conf. Ser.

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“…As shown in Figure 12, a direct mechanism between MATLAB and HSPICE is established to convert the pixels of the input images into digital signals. 49 So, they can be used in the HSPICE for application to the transistors using the CNTFETs library. Besides, the MATLAB role in the presented research is indicated with dark-red dotted lines.…”

Section: Case Study: Image Processing Using Single-bit Comparatorsmentioning

confidence: 99%

SR‐GDI CNTFET‐based magnitude comparator for new generation of programmable integrated circuits

Shiri

Sadeghi

Rafiee

et al. 2022

Circuit Theory & Apps

Self Cite

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Summary The performance of the programmable integrated circuits (ICs) like digital signal processors (DSPs), central processing units (CPUs), and microcontrollers is highly dependent on the magnitude comparators. This article presents a new reliable and efficient 1‐bit comparator based on carbon nanotube field‐effect transistors (CNTFETs) technology. The gate diffusion input (GDI) technique is used to reduce the number of transistors. Also, single swing restoration (SR) transistors and transmission gate (TG) techniques are combined to attain full‐swing outputs with high driving capability. The low internal capacitances and the fewer number of internal nodes of the proposed comparator make it low‐power both in single‐bit and multibit (2‐bit, 4‐bit, 8‐bit, and 16‐bit) implementations. Variations analyses of the circuit and technology parameters are performed that show the cell efficiency. From the layout results, the 1‐bit and 16‐bit comparators occupy 0.1944 μm2 and 37.485 μm2 as the total die area, respectively. The proposed circuit is implemented in image processing in which the best performance compared with state‐of‐the‐art designs regarding hardware complexity, circuitry performance, and image quality assessments are confirmed, by at least 50% improvements of different critical parameters. The resulted figure of merits nominates the cell for future ICs.

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“…Generally, binary multipliers are categorized into two main categories: parallel and serial (iterative) multipliers. In both cases, the optimization of the partial products generation and the summation of the partial products have a big impact on the performance of the multiplier [Rafiee et al, 2021]. Partial products can be generated serially or in parallel by using AND gates at the bit level or by using customized partial products generation (CPPG) cells at higher levels.…”

Section: Introductionmentioning

confidence: 99%

FPGA Implementation of Fast Binary Multiplication Based on Customized Basic Cells

Al-Nounou¹,

Al-Khaleel²,

Obeidat³

et al. 2022

jucs

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Multiplication is considered one of the most time-consuming and a key operation in wide variety of embedded applications. Speeding up this operation has a significant impact on the overall performance of these applications. A vast number of multiplication approaches are found in the literature where the goal is always to achieve a higher performance. One of these approaches relies on using smaller multiplier blocks which are built based on direct Boolean algebra equations to build large multipliers. In this work, we present a methodology for designing binary multipliers where different sizes customized partial products generation (CPPG) cells are designed and used as smaller building blocks. The sizes of the designed CPPG cells are 2×2, 3×3, 4×4, 5×5, and 6×6. We use these cells to build 8×8, 16×16, 32×32, 64×64, and 128×128 binary multipliers. All of the CPPG cells and the binary multipliers are described using the VHDL language, tested, and implemented using XILINX ISE 14.6 tools targeting different FPGA families. The implementation results show that the best performance is achieved when cell 3×3 is used and Virtex-7 FPGA is targeted. The binary multipliers that are designed using the proposed CPPG cells achieve better performance when compared with the binary multipliers presented in the literature. As an application that utilizes the proposed multiplier, a Multiply-Accumulate (MAC) unit is designed and implemented in Spartan-3E. The implementation results of the MAC unit demonstrate the effectiveness of the proposed multiplier.

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An efficient multiplier by pass transistor logic partial product and a modified hybrid full adder for image processing applications

Cited by 15 publications

References 29 publications

Design of 4-bit absolute value detector with low energy

Design of 4-bit absolute value detector with low energy

SR‐GDI CNTFET‐based magnitude comparator for new generation of programmable integrated circuits

FPGA Implementation of Fast Binary Multiplication Based on Customized Basic Cells

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