An efficient method to localize and correct bugs in high-level designs using counterexamples and potential dependence

Matsumoto, Takeshi; Ono, Shohei; Fujita, Masahiro

doi:10.1109/vlsi-soc.2012.6379049

2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC) 2012

DOI: 10.1109/vlsi-soc.2012.6379049

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An efficient method to localize and correct bugs in high-level designs using counterexamples and potential dependence

Takeshi Matsumoto

Shohei Ono

Masahiro Fujita

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Cited by 3 publications

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An efficient method to localize and correct bugs in high-level designs using counterexamples and potential dependence

Cited by 3 publications

References 9 publications

In-Circuit Mutation-Based Automatic Correction of Certain Design Errors Using SAT Mechanisms

In-Circuit Mutation-Based Automatic Correction of Certain Design Errors Using SAT Mechanisms

Improving polynomial datapath debugging with HEDs

A probabilistic approach for counterexample generation to aid design debugging

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