An Efficient Method of Parallel Multiplication on a Single DSP Slice for Embedded FPGAs

Abstract

Field-programmable gate arrays (FPGAs) can efficiently implement custom applications via their embedded digital signal processor (DSP) slices, including binary multipliers. An increasing number of binary multipliers belonging to a DSP slice usually demonstrate that it has the capacity to process as many multiplication operations as possible in one clock cycle. In order to fully utilize the DSP resource, in this paper, we propose a novel DSP slice optimization method to achieve parallel multiplication on single DSP slice, namely PMSDS. First, the PMSDS splits multiplicators into two separate parts, i.e., valid bits and vacant bits, using a customized polynomial algebra method. Then, the PMSDS pre-calculates the maximum number of overflow bits combining the above-mentioned polynomial algebra method. Finally, it computes the total multiplicators' bit numbers and parallel the final multiplicators. We also propose an optimization model to find the best parallel solution according to the performance and precision of a single DSP slice. Moreover, we implement a PMSDS-based matrix multiplication algorithm supporting the computing precision dynamically changing. The experiments based on a large-scale and real-world matrix multiplication show that the PMSDS has better performance in latency and resource utilization than the traditional, add-tree, and full-unroll methods and is more outstanding in frequency and dynamic power consumption comparing with the state-of-the-art methods.

DSP-Packing: Squeezing Low-precision Arithmetic into FPGA DSP Blocks

“…Huang et al [7] propose a method for implementing parallel multiplications on a single DSP slice. On the DSP48E2 that is present on Xilinx UltraScale FPGAs [1], this method allows to implement two multiplications w 0 •a 0 = r 0 and w 1 •a 1 = r 1 and a multiply-accumulate result r 2 = w 0 • a 1 + w 1 • a 0 .…”

A Scalable Architecture for Accelerating Multi-operation and Continuous Floating-point Matrix Computing on FPGAs

“…Therefore, how to allocate and mine DSPs resources seems particularly meaningful. For instance, a method of parallel multiplication for single DSPs was developed to fully exploit the computing potential of DSPs [29].…”